An Implementation

Will try to implement F1, F2, F3 directly, then implement F4 = F1 + F2 + F3

F1 = BC’ + AD’ (use 7451 + inverter, this the 5th inverter)

What about F2?

F2 = A’B’C’D’ + BCD

Do NOT have a 4 input NAND gate????

Need four inverters for A’, B’, C’, D’

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