library ieee;
use ieee.std_logic_1164.all;
use work.cypress.all;

-- ALU for lab 

entity alu4 is
  port (  a,b: in std_logic_vector(3 downto 0);
	  cin : in std_logic;
          func: in std_logic_vector(1 downto 0);
	  cout : out std_logic;
	  y: out std_logic_vector(3 downto 0)
       );


attribute pin_numbers of alu4:entity is

" a(3):2 a(2):3  a(1):4  a(0):5 b(3):6 b(2):7  b(1):8  b(0):9 cin:10 func(1):14 func(0):13 " &
  " y(3):22  y(2):21  y(1):20  y(0):19  cout:18";  


end alu4;

architecture a of alu4 is

 signal b_int : std_logic_vector(3 downto 0);
 signal c_int: std_logic_vector(4 downto 0);

begin

 b_int <= b;
 c_int(0) <= cin;

 cout <= c_int(4);

 process

  begin
  
   case func  is
  
    when "00" => y <= a and b;
    when "01" => y <= a or b;
    when "10" => y <= a xor b;

    when others =>

    for i in 0 to 3 loop
       y(i) <= a(i) xor b_int(i) xor c_int(i);
       c_int(i+1)  <= (a(i) and b_int(i)) or (c_int(i) and (a(i) or b_int(i)));
    end loop;

   end case;

 end process;

end a;