Lab #7: SSN Decoder PRELAB Requirements

Lab #7, the SSN Decoder, is a two week lab. Each week has pre-lab requirements. These requirements are:

1. The first week, you MUST have the schematics and F1,F2,F3,F4 K-MAPS for your discrete simulation ready for TA checkoff at the beginning of the lab period. Since each solution is unique, the TA can only check that you have made a good faith effort at getting a correct solution. You must have a minimized SOP form for F4 from a K-map even if you are implementing F4 as F1 + F2 + F3.

   You must also have your implementation simulated via Altera Maxplus. Look at the ZIP archive on the lab page to see a sample implementation.

2. The 2nd week, you must have a printout of your VHDL code plus a printout of your completed VHDL simulation/JEDEC report page. You must demonstrate to the the TA that the VHDL simulation results matches the expected results for your SSN. If your results are incorrect, then you will not be allowed to use the PLD programmer. The EQUATIONS used in your VHDL code for F1,F2,F3,F4 must be the minimized SOP equations from your K-maps.

The checkoff of BOTH the discrete implementation and the PLD implementation will be done the 2nd week (or earlier if you have them done earlier). The lab report will be due one week after checkoff as is normally required.

It will probably take you most of both lab periods (first and 2nd week) to get your discrete implementation working. If your discrete implementation is not working by the start of the 2nd lab period, then go ahead and get your PLD implementation working FIRST, then use the rest of the 2nd lab period to finish up your discrete implementation.