JK Flip-Flop (rising edge triggered)

C J K Ps Ns0 X X Q Q1 X X Q Q0?1 0 0 Q Q 0?1 0 1 X 00?1 1 0 X 10?1 1 1 Q Q’

J

Q

C

Q’

C is the clock input. J,K inputs are only sampled at a clock edge.

K

Retain State

Synchronous Reset

Synchronous Set

Synchronous Toggle

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