Summary
High level VHDL can let you describe digital systems easier and faster. These descriptions are more understandable to an external reader.
Still MUST KNOW implications of a high level VHDL statement -- ie. What gates get generated?
- Sum <= Cnta + Cntb; Easy to write, but what kind of adder gets synthesized? There are many different ways to build an adder, and each one has a different tradeoff in terms of speed and gate count!
Take EE 4743/EE 6743 to find out more about Digital System design!