VHDL For Three PLD Solution
Up to this time, have been using VHDL to specify boolean equations.
VHDL has high-level statements that allow more natural specification of a problem
Example: What is the boolean equation for signal “D7”? (=1 when dicesum = 7).
VHDL Boolean equation: D7 <= (not dsum(3)) and dsum(2) and dsum(1) and dsum (0);
High level VHDL Statement: D7 <= ‘1’ when (dsum = “0111”) else ‘0’;