Dice Game Implementation
Dice game implemented in three 22V10 PLDs
- control.vhd (Finite State Machine)
- dpatha.vhd (two 1-6 counters, adder)
- dpathb.vhd (point register, comparator, test logic)
The Control FSM is implemented using one-hot encoding.
- Outputs q0, q1, q5 are states S0, S1, S5. Output “win” is state S2, output “lose” is state S3. Outputs q0,q1,q5 are available just for debugging purposes.