EE 3714: Dice Game Lab

The dice game described in Chapter 22 of your textbook is the subject of the last lab of the semester. The game has been implemented in three 22V10 PLDs. Form two person groups for this assignment (there can be a three person group if necessary).  Each group will be given three preprogrammed 22V10 PLDs that implements the three sections of the dice game. You must do the following:

  1. Test each PLD separately and verify that they perform their part of the dice game. This link describes the how the dice game is split among the three PLDs. You MUST also read the information in Chapter 22 of the textbook to understand the operation of the Dice game. The three PLDs will be marked with RED ("control.vhd"), GREEN ("dpatha.vhd"), and BLUE ("dpathb.vhd") to indicate which VHDL files were use to program them.
  2. Hook the three PLDs together to form the complete dice game and verify its operation.

When testing, you will want to use a very slow clock to observe the counter, dicesum outputs. A slow clock will also allow you to stop the dice roll on a particular value in order to force a win or loss condition.

REPORT

There is no report for this lab.  Instead, you must print out this page, and get the following items signed off by your TA:

  1. "control" PLD:  Demonstrate to the TA that you can enter all five states by exercising the inputs.
  2. "dpatha" PLD:  Demonstrate to the TA that the individual counters do indeed count in 1 to 6 sequences.  Explain to the TA exactly why the two counters act as they do.   Also verify that the sum output is the sum of the two count values.
  3. "dpathb" PLD:  Demonstrate how to get each output (EQ, D7, D11, D2312) to go to a '1'.
  4. Complete DiceGame:  Demonstrate the complete dice game to the TA.  Have the dicesum going to four LEDs, and the Win, Lose outputs going to two other LEDs.    Demonstrate both Wins from both states S1, and S5. Demonstrate Losses from both State 1, and State S5.

 

DATES

The 2nd week of the SSN Finite State Machine Lab is the first week of this lab.   You need to find a lab partner, and  get at least one of the above items checked off by the Lab TA in the first week (Nov 15th for non-Monday labs, Nov 22nd for Monday labs that are not caught up with the other sections).    The last week of the semester (Nov 29th), is the 2nd week of this lab.   If you finish the entire lab during the first week, then you do not have to attend the final week of lab.

Grading

This lab is worth twice the points of previous labs.

VHDL Files, Pinouts

These files are for your reference.  Since you are provided preprogrammed PLDs, you do not have to write any VHDL or do simulation. However, the VHDL files may prove interesting to you.  The pinout summary file contains the pinout information of each PLD; you will need this in order to test the PLDs and connect them together.

Last modified: Mon Oct 4 08:11:08 CDT 1999