EE 3713/3714
Digital Devices
Class Policy and Syllabus (Fall '01)

Bob Reese
Simrall 335 - phone: 325-3154
Office Hours Simrall: TThF 2:30-4:00 pm

Email address: reese@ece.msstate.edu

WWW Page: http://www.ece.msstate.edu/~reese/EE3714

Textbooks: Stephen Brown, Zvonko Vranesic: Fundamentals of Digital Logic with VHDL Design

The online notes will be the principle source of information in this class. The textbook serves as a reference; feel free to use other textbooks on Digital Design for reference purposes.

Grade Determination: (EE 3714)
(3) Exams 55% (must get 60% Test+Final average to get a 'D' in course)
(1) Final 20%
Labs/HW 25% (must get 60% LAB grade to be able to get a 'D' in course)
____
100%


Grade assignment is on a 10-point scale. Homework is due at the beginning of the class period. No late homework will be accepted.

If you are in enrolled in EE 3714, then you have a regular Laboratory assignment each week. You MUST get at least a 60% average for your Lab assignments in order to achieve a 'D' grade in this course, REGARDLESS of how well you do on the other material (in-class tests, homework, etc). This is to prevent a student from simply disregarding the lab assignments and concentrating solely on the lecture. You MUST get at least a 60% average for your combined Tests and Final in order to achieve a 'D' grade in this course, REGARDLESS of how well you do on the lab and homework assignments. A student who cannot achieve a passing grade on in-class material cannot pass this course.

ACADEMIC DISHONESTY

Occasionally, we have a problem in this course with Academic Dishonesty. Academic Dishonesty is when you present some other person's work as your own. The following is my definition of academic dishonesty:

• Looking at or copying any material from another student. The person providing this material would also be guilty of academic dishonesty.

You may DISCUSS external homeworks, and verbally answer questions about homeworks from other students. You may not SHOW your homework to another student, or provide an 'old copy' as an example!!!!

If I find a student guilty of academic dishonesty, expect an F in the course and an academic dishonesty claim to go into your permanent academic record.

Syllabus

Course Topics and Order of Coverage

Week 1 (Aug 20) : Number Systems, Binary Arithmetic (Ch 5.1, 5.3.1, 5.3.2)
Week 2 (Aug 27) : Binary Arithmetic, Boolean Algebra (Ch 2.1 thru Ch 2.7)
Week 3 (Sep 3) : Real Gates (Ch 3.1 thru Ch 3.3)
Week 4 (Sep 10 ): Real Gates, Mixed Logic
Week 5 (Sep 17) :Altera Maxplus (Appendix B) Test #1
Week 6 (Sep 24) : Maxterms, Minterms, Kmaps (Ch 4.1 thru Ch 4.6)
Week 7 (Oct 1) : SSN Decoder, PLDs, VHDL (Ch 3.6)
Week 8 (Oct 8): Combinational Building Blocks, (Ch 6.1 thru Ch 6.3)
Week 9 (Oct 15): FFs, Latch Operation, Test #2
Week 10 (Oct 22): Sequential Building Blocks (Ch 7.1 thru Ch 7.9)
Week 11 (Oct 29): General Sequential Design (Ch 8.1 - Ch 8.3)
Week 12 (Nov 5): General Sequential Design, SSN FSM Lab
Week 13 (Nov 12): Dice Game, FPGAs (handouts) Test #3
Week 14 (Nov 19): Arithmetic Ops, System Timing (Ch 5.2, notes)
Week 15 (Nov 26): System Timing
Week 16 (Dec 3): Review for Final