use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
entity myvhdl is
port (CLK: in STD_LOGIC;
RST: in STD_LOGIC;
X: in STD_LOGIC;
Z: out STD_LOGIC);
end;
architecture myvhdl_arch of myvhdl is
-- SYMBOLIC ENCODED state machine:
Sreg0
type Sreg0_type is (S1, S2, S3, S4);
signal Sreg0: Sreg0_type;
begin
--concurrent signal assignments
Sreg0_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RST='1' then
Sreg0 <= S1;
else
case Sreg0 is
when S1 =>
if X='0' then
Sreg0 <= S1;
elsif X='1' then
Sreg0 <= S2;
end if;
when S2 =>
if X='1' then
Sreg0 <= S2;
elsif X='0' then
Sreg0 <= S3;
end if;
when S3 =>
if X='1' then
Sreg0 <= S4;
elsif X='0' then
Sreg0 <= S1;
end if;
when S4 =>
if X='0' then
Sreg0 <= S3;
elsif X='1' then
Sreg0 <= S2;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- signal assignment statements for
combinatorial outputs
Z_assignment:
Z <= '0' when (Sreg0 = S1 and X='0')
else
'0' when (Sreg0 = S1 and X='1') else
'0' when (Sreg0 = S2 and X='1') else
'0' when (Sreg0 = S2 and X='0') else
'0' when (Sreg0 = S3 and X='1') else
'0' when (Sreg0 = S3 and X='0') else
'0' when (Sreg0 = S4 and X='0') else
'1' when (Sreg0 = S4 and X='1') else
'1';
end myvhdl_arch;