Declarations
"clocks
CLK PIN;
"input ports
RST PIN;
X PIN;
"output ports
Z PIN;
"******** BINARY ENCODED state machine: Sreg0 ******
Sreg0_0 NODE istype 'reg';
xilinx property 'save Sreg0_0';
Sreg0_1 NODE istype 'reg';
xilinx property 'save Sreg0_1';
Sreg0_2 NODE istype 'reg';
xilinx property 'save Sreg0_2';
Sreg0 = [Sreg0_2, Sreg0_1, Sreg0_0];
S0 = ^b000;"diagram ACTIONS
S1 = ^b001;
S2 = ^b010;
S3 = ^b011;
S4 = ^b100;
"************* state machine: Sreg0 *************
Equations
" clock signals definitions
Sreg0.clk = CLK;
Sreg0_0.clr = RST;
Sreg0_1.clr = RST;
Sreg0_2.clr = RST;
State_diagram Sreg0
State S0:
Z=^b0;State S1:
IF (!X#RST) THEN
S0
ELSE IF (X&!RST) THEN
S1;
Z=^b0;State S2:
IF (X&!RST) THEN
S1
ELSE IF (!X&!RST) THEN
S2;
Z=^b0;State S3:
IF (!X&!RST) THEN
S0
ELSE IF (X&!RST) THEN
S3;
Z=^b0;State S4:
IF (!X&!RST) THEN
S2
ELSE IF (X&!RST) THEN
S4;
Z=^b1;" end of state machine - Sreg0
IF (X&!RST) THEN
S1
ELSE IF (!X&!RST) THEN
S2;
end seqmoore