Pin Connections of the 84-Pin XS10 and XS10XL

FPGA on the DigilabΤ Board

 

The following table lists the pins of the XCS05 and XCS10 (and XL versions) FPGA as well as the connections on the Digilab board. The pins are available either on the J1, J2 and J3 connectors or the J2 and J3.

 

Before and during configuring the FPGA, all the outputs not used for configuration are tri-stated with the I/O pull-up resistor activated. After the configuration, the unused pins (IOBs) are configured as a input pins with the I/O pull-up resistor activated.

 

 

FPGA XS10 and XS05 [1]

Digilab Connections [2]

Pin No.

Name

Description

Name

Function

1

GND

0V (Ground)

GND

Ground

2

Vdd

+5V or +3.3V for XL

Vdd

Power (5V or 3.3V)

3

I/O

General I/O

PWE

Parallel Prt Write Enable (J1, J3)

4

I/O

General I/O

PD0

Par. Port Data pins (J1,J3)

5

I/O

General I/O

PD1

Par. Port Data pins (J1,J3)

6

I/O

General I/O

PD2

Par. Port Data pins (J1,J3)

7

I/O

General I/O

PD3

Par. Port Data pins (J1,J3)

8

I/O

General I/O

PD4

Par. Port Data pins (J1,J3)

9

I/O

General I/O

PAS

Par. Port Addr. Strobe (J1, J3)

10

I/O,

 

SGCK1 (5V only),

 

 GCK8 (XL only)

SGCK1: One of 4 Secondary Global Inputs driving a global net with minimal delay. An input pad connected to the BUFGS symbol is automatically connected to one of these pins. If buffers are not used, the pin is a general I/O.

GCK8: One of 8 global inputs driving a dedicated net with short delays. If not used the pins are general I/Os. An input pad connected to the  BUFGLS symbol is automatically connected to one of these pins.

PRS

Parallel Port Reset (J1, J3)

11

Vdd

+5V or +3.3V for XL

Vdd

 

12

GND

Ground

GND

 

13

I/O,

 

PGCK1 (5V only),

 

GCK1 (XL only)

PGCK1: One of 4 Primary Global Inputs driving a global net with minimal delay. An input pad connected to the BUFGP symbol is automatically connected to one of these pins. If buffers are not used, the pin is a general I/O.

GCK1: One of 8 global inputs driving a dedicated net with short delays. If not used the pins are general I/Os. An input pad connected to the  BUFGLS symbol is automatically connected to one of these pins.

CLK1

Clock  1

14

I/O

 

PDS

Par. Port Data Strobe (J1, J3)

15

I/O, TDI

TDI: used for boundary scan or General I/O

PWT

Par. Port Wait/Busy (J3)

16

I/O, TCK

Used for boundary scan or General I/O

PD5

Par. Port Data pins (J1,J3)

17

I/O, TMS

Used for boundary scan or General I/O

PD7

Par. Port Data pins (J1,J3)

18

I/O

 

PD6

Par. Port Data pins (J1,J3)

19

I/O

 

SW8

Gen Purpose Switch (J1)

20

I/O

 

SW7

Gen Purpose Switch (J1)

21

GND

Ground

GND

 

22

Vdd

+5V or +3.3V for XL

Vdd

 

23

I/O

 

SW6

Gen Purpose Switch (J1)

24

I/O

 

SW5

Gen Purpose Switch (J1)

25

I/O

 

SW4

Gen Purpose Switch (J1)

26

I/O

 

SW3

Gen Purpose Switch (J1)

27

I/O

 

SW2

Gen Purpose Switch (J1)

28

I/O

 

SW1

Gen Purpose Switch (J1)

29

I/O, SGCK2 †, GCK2 ††

See pin 10

O1

User configurable I/O (J1, J2)

30

Not Conn. (5V), M1 (3.3V)

On 5V: not connected.

XL: Mode pin

M1_NC

FPGA Conf. pin

31

GND

 

GND

 

32

MODE (5V), M0 (XL)

On 5V: Mode.

XL: Mode pin

MODE

FPGA Conf. pin

33

Vdd

+5V or +3.3V for XL

Vdd

 

34

Not Conn (5V), /PWRDWN (3.3V)

XL: Active low, when this pin is low, the FPGA goes into Power Down state. When /PWRDWN goes high the FPGA becomes operational

M2_NC

FPGA Conf. pin

35

I/O, PGCK2 †, GCK3 ††

see pin 13

CLK2

Clock 2 (J1)

36

I/O (HDC)

During configuration is driven high. After config. is a general I/O

O2

User configurable I/O (J1, J2)

37

I/O (/LCD)

During configuration is driven low. After config. is a general I/O

O3

User configurable I/O (J1, J2)

38

I/O

 

A4

Anode A4 of 7-segmt 1(J1)

39

I/O

 

A3

Anode A3 of 7- segmt 1(J1)

40

I/O

 

A2

Anode A2 of 7- segmt 1(J1)

41

I/O (INIT)

Used during config; after config is a general I/O

INIT (O4)

Conf./User configurable I/O J1, J2)

42

Vdd

+5V or +3.3V for XL

Vdd

 

43

GND

Ground

GND

 

44

I/O

 

A1

Anode A1 of 7- segmt 1(J1)

45

I/O

 

CG

Segm G of 7-segm Dsp (J1)

46

I/O

 

CF

Segm F of 7-segm Dsp (J1)

47

I/O

 

CE

Segm Ef of 7-segm Dsp (J1)

48

I/O

 

CD

Segm D of 7-segm Dsp (J1)

49

I/O

 

CC

Segm C of 7-segm Dsp (J1)

50

I/O

 

CB

Segm B of 7-segm Dsp (J1)

51

I/O, SGCK3 †, GCK4 ††

see pin 10

CA

Segm A of 7-segm Dsp (J1)

52

GND

Ground

GND

 

53

DONE

Config.

DONE

FPGA Conf. pin

54

Vdd

+5V or +3.3V for XL

Vdd

 

55

/PROGRAM

Initiates config.

PROG

FPGA Conf. pin

56

I/O (D7: XL only )

Used during configuration; afterwards is a general I/O

BTN4

Push button (J1)

57

I/O, PGCK3 †, GCK5 ††

see pin 13

BTN3

Push button (J1)

58

I/O (D6 ††)

see pin 56

BTN2

Push button (J1)

59

I/O (D5 ††)

see pin 56

BTN1

Push button (J1)

60

I/O

 

LD8

LED8 (J1)

61

I/O (D4 ††)

see pin 56

LD7

LED7 (J1)

62

I/O

 

LD6

LED6 (J1)

63

I/O

 

Vdd

 

64

GND

 

GND

 

65

I/O (D3 ††)

see pin 56

LD5

LED5 (J1)

66

I/O

 

LD4

LED4 (J1)

67

I/O (D2 ††)

see pin 56

LD3

LED3 (J1)

68

I/O

 

LD2

LED2 (J1)

69

I/O (D1 ††)

see pin 56

LD1

LED1 (J1)

70

I/O

 

LDG

Latch Enable LED driver (J1)

71

I/O (D0 ††, DIN)

see pin 56

DIN (O5)*

Conf./User configurable I/O  (J1,J2)

72

I/O, SGCK4 †, GCK6 ††, (DOUT)

see pin 10

DOUT (RXD)

FPGA Conf pin/RS232 Receive signal (J2)

73

CCLK

Config. Clock (Input in Slave mode and Output in Master Mode)

CCLK

FPGA Conf. pin

74

Vdd

+5V or +3.3V for XL

Vdd

 

75

O, TDO

Boundary scan: Test Data Out

TDO(TXD)

FPGA Conf pin/RS232 Transmit signal (J2)

76

GND

Ground

GND

 

77

I/O

 

R

VGA Red  (J2)

78

I/O, PGCK4 †, GCK7 ††

see pin 13

G

VGA Green (J2)

79

I/O (CS1 ††)

Config.

B

VGA Blue (J2)

80

I/O

 

VS

VGA Vertical Sync. (J2)

81

I/O

 

HS

VGA Horizontal Sync (J2)

82

I/O

 

PS2C

PS2 Clock signal (J1,J2)

83

I/O

 

PS2D

PS2 Data signal (J1,J2)

84

I/O

 

PINT

Par. Port Interrupt (J1,J3)

†: For the 5V FPGA only

††: For the 3.3V XL FPGA only

* Italicized names: Dual purpose pins: the first name is the Xilinx function and the second one gives the Digilab’s function

 

References

 

  1. Xilinx Databooks: Spartan and Spartan XL FPGA data sheet, Xilinx, Inc, 2000
  2. Digilab XL Users Manual, Digilent, Inc. Pullman, WA (http://www.digilent.cc/XLAusersmanual.pdf ) or the Digilent website (http://www.digilent.cc/)

 

Back to Digilab Board description; back to EE201 webpage.

Created by J. Van der Spiegel Sept. 2001; updated Nov. 3, 2001.