a non-resetting sequence recognizer
The following state diagram (Fig. 1) describes a finite state machine
with one input X and one output Z. The FSM asserts its output Z when it
recognizes the following input bit sequence: "1011". The machine will keep
checking for the proper bit sequence and does not reset to the initial
state after it has recognized the string. As an example the input string
X= "..1011011..." will cause the output to go high twice: Z = "..0001001.."
. The output will asserts only when it is in state S4 (after having seen
the sequence 1011). The FSM is thus a Moore machine.
Figure 1: State diagram, describing the sequence detector implemented as a Moore machine. The number in italics underneath the states indicate which part of the sequence the state remembers.
This state diagram can be described in ABEL code given in Listing 1. The output is described after the STATE Si: statement.
Listing 1: ABEL source code for the Moore machine implementation of the sequence detector described in Fig. 1
X, CLOCK, RST
PIN;
Z PIN istype
'com';
Q2, Q1, Q0
PIN istype 'reg';
"State register declarations
SREG = [Q2,Q1,Q0];
S0 = [0,0,0];
S1 = [0,0,1];
S2 = [0,1,0];
S3 = [0,1,1];
S4 = [1,0,0];
Equations
"Definition
of the state machine clock signal
[Q2,Q1,Q0].AR
= RST;
[Q2,Q1,Q0].CLK
= CLOCK;
"Define state
diagram
STATE_DIAGRAM
SREG
STATE S0: Z=0;
Figure 2: Simulation of the sequence detector (for "1011") described with the state diagram of Fig. 1. (Screen clip from Xilinx XACTstep(TM) Foundation software)
One notices that the output asserts after the input sequence 1011 as specified.