Finite State Machine implemented as a Moore Machine:

a non-resetting sequence recognizer

The following state diagram (Fig. 1) describes a finite state machine with one input X and one output Z. The FSM asserts its output Z when it recognizes the following input bit sequence: "1011". The machine will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the string. As an example the input string X= "..1011011..." will cause the output to go high twice: Z = "..0001001.." . The output will asserts only when it is in state S4 (after having seen the sequence 1011). The FSM is thus a Moore machine.
 

Figure 1: State diagram, describing the sequence detector implemented as a Moore machine. The number in italics underneath the states indicate which part of the sequence the state remembers.

This state diagram can be described in ABEL code given in Listing 1. The output is described after the STATE Si: statement.

Listing 1: ABEL source code for the Moore machine implementation of the sequence detector described in Fig. 1

The corresponding simulation is shown in Figure 2.


 

Figure 2: Simulation of the sequence detector (for "1011") described with the state diagram of Fig. 1. (Screen clip from Xilinx XACTstep(TM) Foundation software)

One notices that the output asserts after the input sequence 1011 as specified.


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Created by J. Van der Spiegel: November 16, 1997. Updated by J. Van der Spiegel, May 17, 2000.