VHDL methods

Analysis, compilation and elaboration

The simulation process of VHDL entities requires two preliminary steps:

• compilation
• simulation

The source code analysis involves the lexicographical and the syntaxical analysis. If both the lexis and the syntax are correct the compiler generates an intermediary code stored in the design library.

There are several kinds of design libraries:

• work library; where the designer puts "by default" the compiled descriptions
• IEEE library; where the designer finds standard logic system and the corresponding types and functions
• user defined libraries; where the designer puts specific types of compiled components (library CMOS_gates;)

The next step is elaboration which performs several actions such as:

• hierarchical expansion of design hierarchy (components within components),
• elaboration of generics and declarative parts; this action creates a generic constant of the indicated type for each of the generics,
• binding of components; this action binds components to architectures,
• storage allocation of objects; this action allocates memory storage for the various objects,
• initialization values of objects; this action initializes the user defined values

The simulation process starts with several initializing actions such as:

• computation of explicit signals; the signals in ports and architectures are initialized, resolved and assigned values
• processes are executed until the suspension on an explicit or implicit wait statement
• simulation time is reset to 0 (now = 0 ns)

The following figure shows different elements and actions required before the simulation process can start.

Simulation

Simulation is the essential process required for any design. It is the process which permits to verify the functional characteristics of models at any level of detail and/or abstraction; from system level down to gate level. Simulators use timing characteristics defined before synthesis. After the synthesis the simulation is run using the temporal parameters extracted from the layout. Such a simulation allows dynamic timing analysis. Static timing analysis may also be done by synthesis tools during optimization by simply extracting the delays from the cells used to generate the circuit.

However static analysis is difficult to apply for:

• complex clocking structures with multiple clocks
• asynchronous circuits and interfaces with asynchronous circuits
• and in general for the circuits with multiple delay paths

The main role of simulation is the model animation. This allows modeler to observe each unit (entity) response according to the applied stimuli. Given that the models may be built from many interconnected units, the simulation offers the means to observe and o analyze the internal activities visible at the interconnection level.

Simulator interface

A typical VHDL simulator handles several kinds of windows used to display the simulation results. The following figures show some working windows of Modeltech simulator. The owner of the software is ModelTechnology company.

• transcript window is used to read the commands and to display the reports (for example: assert report).

• signals and variables windows may visualize the state of the selected signals and variables

• the wave window illustrates the evolution of the selected signal values

• dataflow window allows to see the input/output signals of the simulated model

• structure window illustrates the configuration of the simulated model

• source window allows to see the source code of the simulated circuit, to trace symbolically the simulation, and to install the breakpoints at source level

Fault simulation

Fault simulation is the simulation of the model with a particular set of input stimuli vectors.

Fault simulation allows to:

• detect the errors in the parts of the circuits not being functionally tested by test vectors
• check the quality of test vectors
• perform both on-board and in-circuit testing

The efficiency of functional testing is called fault coverage and is measured by:

Typical value of fault coverage may be situated between 75% and 99.9%; some faults are always possible !

The cost of "repairing" of a functional error is changing rapidly depending on the stage and place of the error detection.

Synthesis

Synthesis is a process of transforming the functional models into the detailed structural models.

There are two levels of digital circuits synthesis:

• high level synthesis where the algorithms are mapped onto register transfer architectures
• register transfer synthesis where RTL model is mapped into the functionally corresponding gate level structure

High level synthesis proceeds in several steps:

• algorithm transformation : removing redundancies, loops unroll, constant propagation, ...
• CDFG generation : input description is transformed into Control-Data Flow Graph which is the internal form of synthesizer

The CDFG is made of two graphs: the DFG for the data dependencies and the CFG for the control. A synthetizable VHDL code is made of concurrent processes. Normally, one CFG is created by process. A global DFG is added to allow the differenet processes to share the ressources.

• scheduling

The CDFGs contain all the control and data dependencies of a givel behavioral model. Scheduling algorithms partition the CDFG into subgraphs where each subgraph is executed in one control step. Each control step corresponds to one state of the controlling finite state machine. Within a control step, a separate functional unit is required to execute each operation assigned to that step. Scheduling a sequencing graph determines the concurrency of the resulting design, and therefore it affects its performance. By the same way, the maximum number of concurrent operations of a given type during the schedule is a lower bound on the number of required hardware resources. In this way the choice of a schedule affects the area (silicon surface) of the implementation.

There are several algorithms used for scheduling:

• ASAP - As Soon As Possible
• ALAP - As Late As Possible
• List Scheduling
• Force Directed Scheduling

Their efficiency depends on the application type and on the additional scheduling constraints, for example, related to the resource availability.

• allocation

Allocation is used to allocate different kinds of resources to the scheduled execution phases. Normally, it is performed into three steps:

• functional units allocation
• registers allocation
• interconnectionallocation

Allocation algorithms generate data-path structure built from interconnected functional units and registers.



The above example shows how two functional units are allocated to perform four addition operations in two scheduled steps: S₁ and S₂.

• RTL code generation

The final phase of high level synthesis is RTL code generation. This code describes the synthesized circuit in terms of architectural elements characteristic for the RTL level.

Register Transfer Level synthesis

RTL synthesis transforms the RTL level descriptions into the corresponding and optimized gate level models.

This process includes translation and optimization.

• translation provides the gate netlist
• optimization provides an optimized gate netlist

The logic level model is a structural description built from logic gates corresponding to logic operators seen as components

The optimization phase occurs at all intermediate levels (RTL, logic, gate). The constraints provided by the modeler are used to guide the optimization process. The initially generated logic gate net-list undergoes optimization process according to two kinds of constraints:

• minimum size (minimum number of gates)
• minimum delay

The default optimization target is minimum circuit size. This optimization involves the use of hierarchical blocks optimized starting from the lower level blocks in a bottom-up process.

Logic optimization

Once synthesis has translated a design to logic level, all elements seen at RTL level are fixed and only combinational logic is optimized. Optimization at this level performs boolean optimization based on different techniques such as:

• minimization: reduction of terms: e.g. x = dc + c => x = c
• equation flattening: conversion of multiple boolean eqautions into a two-level sum-of-products form
• equation factorization: process of adding intermediate terms in order to reduce the total number of operators ; factorization may induce longer delays.

The synthesis algorithms operate on multiple level (levels of logic equations) and multiple output basis. They are much more complex and efficient than the traditional methods based on a two dimensional Karnaugh maps.

Example of a two-output function of four arguments: x=f(a,b,c,d); y=f(a,b,c,d)

s = a*b*c

x = s + a*b*d

y = a*b + c + d

after factorization => (6 basic gates)

t = a*b

s = t*c

x = s + t*d

y = t + c + d

after flattening =>

x = a*b*c + a*b*d

y = a*b + c + d

and after factorization => (4 basic gates)

t = a*b

r = c + d

x = t*r

y = t + r

Gate level optimization

Gate level optimization is related to the gate to transistor mapping. In this process basic logic gates are mapped onto ASIC or FPGA cells. These cells are built from interconnected transistors in this way that negated operations such as nand or nor need less transistors than direct operators such as and or or. The following example illustrates both the logic level and the gate level optimization. Note that simple gates are replaced by a smaller number of gates including nand and nor. Morover, these functionally more complex cells require less transistors to be realized.

• and and or gates require 6 transistors;
• nand and nor gates require 4 transistors
• not gate needs 2 transistors

Calculate the number of transistors necessary for each scheme?

Block based system development

The synthesis of large systems shifts in the design paradigm from the top-down synthesis to the reusable block-based synthesis. Currently, most functional blocks are created from scratch and are seldom used again. This must change if we wish to sustain the productivity following the growh of complexity. The following figure shows the emerging gap between the productivity and the complexity of the chips.

Note that the reuse is already exploited at the standard cell level. However it is still limited to cell libraries from single supporters.

The reuse paradigm needs reusable blocks and methodologies allowing to combine the blocks coming from different sources into complex systems. The reuse methodology needs also to provide the techniques to create highly reusable or adaptable blocks.

This requires the standards to support the creation and integration of reusable blocs.

The group, known as the VSI Alliance (Virtual Socket Interface) has been created recently. It seeks to define the form and content of information necessary to pass from the creators of the reusable blocks to the users. The Alliance comprises

• intellectual property (IP) providers
• electronic design automation (EDA) companies
• system design companies
• semiconductor foundries

The main aim of the Alliance is to develop the interface standards that allow to mix and match of reusable blocks at software, firmware and hardware level.

In reality a combination of these levels may be used to assemble the final systems.

The above component modeling cube shows three essential dimensions to be taken into account for component modeling:

• level of expression (soft, firm, hard)
• level of precision (causal, clock related, delay related)
• level of flexibility (configurable, generic, closed)

Adaptability

• Soft blocks are flexible and implementation process independent. The disadvantage of soft blocks is that their performance and size are not known.
• Hard blocks are implemented through the layout and optimized for performance; they offer no flexibility - they are closed.
• Firm blocks, expressed as logic or gate netlists, offer a compromise between soft and hard. More flexible and adaptable than hard blocks, they are more predictive of size and performance than soft blocks.

Portability

• Soft blocks are completely portable accross different foundries and kinds of technology.
• Firm blocks are portable accross similar libraries which may be mapped on different technological processes.
• Hard blocks are not portable to different technologies; they are process dependent.

The system design with reusable blocks is going to enforce bottom-up design paradigm. This paradigm will be strictly related to the notion of generations.

Design steps:

• the first design step : decide what are the extensions/modification required for the next generation system
• the second step : look for the required functions/components accross the libraries of reusable the available components;
• the third step : adapt the reusable components (through genericity and configurability)
• the fourth step : integrate the adapted components into the next generation system.

Block based System-On-a-Chip design (SOC)

The integration platform for a System-On-a-Chip design is based on reuse of the predesigned blocks conceived for a required application domain. The selection of the application domain is based on market objectives, and the domain is conceived to permit a high probabilitry of reuse over a certain period of time.

The integration platform consists of:

bus structure, clocking scheme design, I/O configuration, the IP blocks required, the performance required, constraint ranges associated with IP blocks

precharacterized, preverified IP blocks, presteged on the target technology to meet the constraint ranges specified in the integration structure

a set of proven, documented block-authoring and chip integration design methodologies consistent with the models used for IP blocks and scripted for rapid assembly of the SOC. These methodologies provide the support for the design verification, planning and integration of new logic and legacy blocks.

The SOC methodologies

The SOC design-methodology is in a rapid transition from traditional time drived design to Virtual Components based design. This transition is based on the growing defree of reuse.

There three basic levels of reuse:

• personal reuse (small team)
• organizational reuse (source blocks and architectured re-usable blocks)
• global reuse (independent IP providers and integrators, standard virtual components)

The level of reuse depends on the type of the blocks provided for reuse: soft-RTL, firm- netlist, or hard - layout.

Personal reuse

The personal reuse is base on the knowledge and experience accumulated by single designers or small design teams. To make this reuse level effective, derivative projects must involve a high degree of "internal " reuse.

Organizational reuse

The organizational reuse may be based on source reuse portofolio. The entry point into block-based design brings opportunity to reuse the blocks created by another design team. The function, constraints and the context for a block are known as a result of a top-down system design process. Source blocks may be modified to meet the system constraints.

The productivity increase depends in high extent on the quality of documentation, the presence of appropriate testbenches and the availability of the original designer to answer the questions.

Further improvement in organizational reuse may be experienced when:

• the number of blocks is significant,
• blocks are accessible in soft, firm and hard form,
• blocks are provided with complete test benches,
• blocks are documented for reuse in different contexts,
• in-house blocks are integrated with third-party IP block ,
• new management processes are introduced to foster organizational reuse

Global reuse

Global reuse is based on virtual component portofolio. The transition of re-usable block into virtual comonent status is where the greatest productivity benefits are realized. In case of virtual components the separation of authoring and integration is necessary.

Virtual components are are precharacterized and verified blocks designed for specific SOC application domains.

Virtual components are predestined for the development of virtual systems (VS). Virtual systems involve a range of constraints related with performance, power, interconnectivity, relaiability, manufacturability, cost and other market-specific parameters.

The virtual component domains are characterized by the functions, formats, and flexibility (adaptability) of each block, the integration architecture into which the blocks will plug, the techniques required for the evaluation and verification of all constraints affecting the blocks.

Firm and hard virtual components belonging to the given application domain are tuned (power, perfoirmance,cost) and optimized for an integration and manufacturing environment including tools and fabrication processes.

The use of such components may result in huge benefits in design process and allow much shorter TTM.

Things to come

With the maturing of technological processes and the standardization of synthesis techniques and tools, soft VCs will assume an expanding role.

The intercompany methodologies will emerge to provide global IP-based business model for IP control and protection.

Mixed-signal solutions involving the creation of analog and digital VCs will appear. This in turn will promote the reuse of mixed analog-digital blocks on the same chip.