Simple RAM memory
block Simple RAM memory
block
synthetisable description with COMPASS ASIC synthetizer
prepared by P. Bakowski
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.NUMERIC_STD.all; -- contains conversion function to_integer
entity MEM1 is generic(n:POSITIVE:=5);
port(clk,rd,wr:in STD_ULOGIC;ad:in UNSIGNED(n-1 downto 0); data:inout STD_LOGIC_VECTOR(7 downto 0));
end MEM1;
architecture FIRST of MEM1 is
begin
process -- combinational process ! (no internal state to modify the behavior of the architecture)
type TM is array(NATURAL range 0 to 2**ad'length-1) of STD_LOGIC_VECTOR(data'range);
variable m:TM;
begin
wait until clk='1'; -- by default the bus is set to Z
data<=(others=>'Z');
if wr='1' then
m(TO_INTEGER(ad)):=data; -- memory write
elsif rd='1' then
data<= m(TO_INTEGER(ad)); --
end if;
end process;
end FIRST;
