Simple state machine

synthesisable description with COMPASS ASIC synthetizer

prepared by P. Bakowski

package P is

type ST is (S0,S1,S2,S3);

end P;

use work.P.all;

entity FSM is

port(clk:in BIT;rst:in BIT;state:out ST);

end FSM;

architecture FIRST of FSM is

begin

process(clk,rst) -- sequential process

variable vs:ST;

begin

if rst='1' and rst'event then

vs:=S0;

state<=S0;

end if;

if clk='1' and clk'event then

case vs is

when S0 => vs:=S1;state<=S1;

when S1 => vs:=S2;state<=S2;

when S2 => vs:=S3;state<=S3;

when S3 => vs:=S0;state<=S0;

end case;

end if;

end process;

end FIRST;

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