7

prepared by P. Bakowski

Introduction

Contents: specification , requirements, development, package, RAM component, incrementer component, system

RTL level system "specification"

Requirements

package STSL is type MVL is ('0','1','Z');
type MVL_V is array (NATURAL RANGE <> )of MVL;
function BUSFUNC(INPUT: MVL_V) return MVL; -- resolution function
subtype TSL is BUSFUNC MVL;
type TSV is array (NATURAL RANGE <>) of TSL;
end STSL;
package body STSL is
function BUSFUNC(input: MVL_V) return MVL is -- bus resolution function !!!
variable resolved_value: MVL:='Z';
variable state:MVL:='Z';
begin
for i in input'range loop
if input(i)/='Z' then
resolved_value:= input(i);
assert state='Z'
report "signal conflict in BUSFUNC"
severity warning; state:=input(i);
end if;
end loop;
return resolved_value;
end BUSFUNC;
end STSL;

The BUSFUNC displays a message if more then one active signal sources ('0' or '1') are detected.
 

Development path

Use the above package to design a small system with 2 components:

• RAM memory entity : 16 words of 16 bits,
• incrementer entity used to increment the contents of all RAM memory words.
• add the type MOT et ADRESSE to the package.
• simulate separately the described entities.
• simulate the system.

Example of complet  package STSL:

package STSL is

type MVL is ('0', '1', 'Z');

type MVL_V is array (NATURAL range<>) of MVL;

subtype MOT is BIT_VECTOR(15 downto 0);

subtype ADRESSE is BIT_VECTOR(3 downto 0);

function BUSFUNC(INPUT: MVL_V) return MVL;

function increment(val : BIT_VECTOR) return BIT_VECTOR;

function to_int(bv : bit_vector) return integer;

subtype TSL is BUSFUNC MVL;

type TSV is array(NATURAL range<>) of TSL;

subtype MOT_R is TSV(15 downto 0);

function to_bit(mr : MOT_R) return MOT;

function to_MVL(mv : MOT) return MOT_R;

end STSL;

package body STSL is
function BUSFUNC(input: MVL_V) return MVL is
variable resolved_value: MVL:='Z';
variable state: MVL := 'Z';
begin
for i in input'range loop
if input(i)/='Z' then
resolved_value:=input(i);
assert state='Z'
report "signal conflict in BUSFUNC"
severity warning;
state :=input(i);
end if;
end loop;
return resolved_value;
end BUSFUNC;

function increment(val : bit_vector) return bit_vector is

alias input : bit_vector(val'length downto 1) is val;

variable result : bit_vector(input'range) := input;

variable carry : bit := '1';

begin

for i in input'low to input'high

loop

result(i) := input(i) xor carry;

carry := input(i) and carry;

exit when carry = '0';

end loop;

return result;

end increment;

function to_int(bv : bit_vector) return integer is

variable result : integer := 0;

begin

for i in bv'range

loop

result := result * 2;

if (bv(i) = '1') then

result := result + 1;

end if;

end loop;

return result;

end to_int;

function to_bit(mr : MOT_R) return MOT is

variable m: MOT;

begin

for i in mr'range

loop

case mr(i) is

when '0' => m(i) :='0';

when '1' => m(i) :='1';

when 'Z' => m(i) :='0';

end case;

end loop;

return m;

end to_bit;

function to_mvl(mv : MOT) return MOT_R is
variable m: MOT_R:="ZZZZZZZZZZZZZZZZ";
begin
for i in mv'range
loop
case mv(i) is
when '0' => m(i) :='0';
when '1' => m(i) :='1';
end case;
end loop;
return m;
end to_mvl;
end STSL;

RAM memory entity

• ABUS: address bus - 4-bits wide
• SEL: selection signal - when is '0' the data bus output is set to high impedance
• RW: read-write signal - when '0' write function is selected

and one input-output

• DBUS: data bus - 16-bit wide, set to high impedance when RAM block is not selected

use work.STSL.all;

entity RAMBIS is

generic(RDEL, SDEL: time := 10 ns);

port (DBUS: inout MOT_R; ABUS : in ADRESSE; SEL,RW: in BIT);

end RAMBIS;

architecture SIMPLE of RAMBIS is

begin

process (SEL)

type MEMORY is array(0 to 15) of MOT;

variable MEM: MEMORY;

begin

if SEL ='1' then

if RW = '0' then

MEM(to_int(ABUS)) := to_bit(DBUS);

else

DBUS <= to_mvl(MEM(to_int(ABUS))) after RDEL;

end if;

else

DBUS <= "ZZZZZZZZZZZZZZZZ" after SDEL;

end if;

end process;

end SIMPLE;

Incrementer entity

• ABUS: address bus - 4-bits wide
• SEL: selection signal - when is '0' the RAM block data bus output should be set to high impedance
• RW: read-write signal - when '0' write function is required

one input:

• Go: starts the counting when set to '0'

and one input-output:

• DBUS: data bus - 16-bit wide

use work.STSL.all;
entity INCREMENTER is
port(dbus: inout MOT_R; abus: out add; RW: out bit;Go: in bit);
end INCREMENTER;

architecture SIMPLE of INCREMENTER is
begin
process
variable compteur: BIT_VECTOR(0 to 3) :="0000";
variable tampon: MOT;
begin
if go = '0' then
boucle1 :
loop
rw<='1';
abus<=compteur;
wait for 20 ns;
tampon:=to_bit(dbus);
tampon:=increment(tampon);
rw<='0';
dbus<=to_mvl(tampon);
compteur:=increment(compteur);
end loop;
end if;
end process;
end SIMPLE;

System entity

use work.STSL.all;
entity SYSTEM is
port(Go : in bit; SEL : in bit);
end SYSTEM;

architecture STRUCTURE of SYSTEM is
component RAMBIS
port(DBUS: inout MOT_R; ABUS : in ADRESSE; SEL,RW: in BIT);
end component;
component INCREMENTER
port(dbus: inout MOT_R; abus: out ADRESSE; RW: out bit;Go: in bit);
end component;
signal donneebus : MOT_R := "ZZZZZZZZZZZZZZZZ";
signal adressebus : ADRESSE;
signal readwrite : bit;
-- there is no configuration section for the above components
-- only one architecture is provided for each component
begin
comp1 : RAMBIS
port map (DBUS=>donneebus, ABUS=>adressebus, SEL=>sel, RW=>readwrite);
comp2 : INCREMENTER
port map (DBUS=>donneebus, ABUS=>adressebus, RW=>readwrite, GO=>go);
end STRUCTURE;