12C12CVHDL based configurable models
prepared by P. Bakowski
Contents: component configuration, configuration module, adder configuration, adder architecture, exercises
The configuration task means the selection of the sub-modules in order to construct the required top-level model. The selection of the sub-modules is done through the configuration parameters. These parameters must be prepared on a deep understanging of the functions provided by the available modules.
The configuration may be performed with closed or generic components. The configured model may be closed or generic. Note that in this sense genericity and configurability are orthogonal concepts and mechanisms.
When several types architectures are defined for a given entity the compiler must know the precise name of the required architecture. In order to select the required architecture VHDL provides configuration modules and configuration statements.
The configuration statement looks as follows:
for instance_name: component_name
use entity working_library_name.entity_name(architecture_name);
Possible configurations for RAM block :
for RAM_1: RAM_block use entity work.RAM_block(functional); -- algorithmic
for RAM_2: RAM_block use entity work.RAM_block(logical); -- compatible
for RAM_3: RAM_block use entity work.RAM_block(vital_level); -- precise
The complex structural descriptions incorporate several components. These components may have only one or several architectures. In order to select one of the possible architecture we use configuration statement or configuration module.
An example of a configuration statement was given above. The following is the presentation of configuration module.
configuration conf_adder of adder is
for structural
for all: xorg use entity work.xorg(only); -- goto only architecture
end for;
for and1: andg use entity work.andg(first); -- goto first architecture
end for;
for and2: andg use entity work.andg(second); -- goto second architecture
end for;
for all: org use entity work.org(only); -- goto only architecture
end for;
end for;
end conf_adder;
This configuration module presented above configurates the adder entity built from several logic gates. The adder architecture is structural. The instantiated gates are chosen from the bgates package illustrated below.
Note that the package contains 3 versions of the architecture for the and gate: architecture only .., architecture first.. and architecture second...
The configuration module called conf_adder is used to chose architecture first for the first and gate instantiation (and1), and the architecture second for the second and gate instantiation (and2).
The org and xorg gates are all instantiated using the same architecture (architecture only ..)
An example of a package with the components necessary to build the structural architecture of adder entity:
-- package with component declarations
package bgates is
component andg
generic (tpd_hl : time := 1 ns; tpd_lh : time := 1 ns);
port (in1, in2 : in bit; out1 : out bit);
end component;
component org
generic (tpd_hl : time := 1 ns; tpd_lh : time := 1 ns);
port (in1, in2 : in bit; out1 : out bit);
end component;
component xorg
generic (tpd_hl : time := 1 ns; tpd_lh : time := 1 ns);
port (in1, in2 : in bit; out1 : out bit);
end component;
end bgates;
generic (tpd_hl : time := 1 ns; tpd_lh : time := 1 ns);
port (in1, in2 : in bit; out1 : out bit);
end andg;
-- the only architecture responds with different delays for low to high and high to low transitions
begin
p1: process(in1, in2)
variable val : bit;
begin
val := in1 and in2;
case val is
when '0' => out1 <= '0' after tpd_hl;
when '1' => out1 <= '1' after tpd_lh;
when others => out1 <= val;
end case;
end process;
end only;
-- the first architectures involves no explicit timing
begin
p1: process(in1, in2)
begin
out1 <= in1 and in2;
end process;
end first;
-- the second architectures involves maximum output delay
architecture second of andg is
begin
p1: process(in1, in2)
variable val : bit;
begin
if tpd_hl> tpd_lh then
out1 <= in1 and in2 tpd_hl;
else
out1 <= in1 and in2 tpd_lh;
end if;
end
