VHDL signals
The VHDL signals are the essential element of the VHDL language.
The VHDL signals allow to represent the contents of the connections
and the data carriers during the simulation process.
Different information types may be carried by the signals :
the BITs,
the INTEGERs,
the BIT_VECTORs and others.
signal a,b: BIT;
a <= a and b; -- signal assignment