VHDL arrays and records

prepared by P. Bakowski


This page describes the arrays and records.

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Arrays

An array in VHDL is an indexed collection of elements all of the same type.

Arrays may be one-dimensional (with one index) , multi-dimensional ( with a number of indices) constrained, in which the bounds for an index are established when the type is defined, or unconstrained, in which the bounds are established subsequently.

type mot is array (31 downto 0) of bit;

type RAM is array (address) of word;

type register_bank is array (byte range 0 to 32) of integer;

An example of an unconstrained array type declaration:

type b_vector is array (integer range <>) of bit;

The symbol <> called a box index range, which will be filled in later when the array type is used.

For example, an object might be declared to be a vector of 32 elements by giving its type as:

b_vector(0 to 31)

a_vector(31 downto 0)

There are two predefined array types, both of which are unconstrained.

They are defined as:

type string is array (positive range <>) of character;

type bit_vector is array (natural range <>) of bit;

The types positive and natural are subtypes of integer .

The type bit_vector is particularly usefull for the modeling of Register Transfer Level representations of digital systems.

An element of an array object can referred to by indexing the name of the object.

Suppose reg and mem are one- and two-dimensional array objects respectively.

Then the indexed names reg(1) and mem(1,1) refer to elements of these arrays.

A contiguous slice of a one-dimensional array can be referred to by using a range as an index.

Sometimes you may need to write a literal value of an array type.

This can be done using an array aggregate, which is a list of element values.

Suppose we have an array type declared as:

type a is array (3 downto 0) of character;

and we want to initialise or write a value of this type containing the elements `f', `o', `o', `d' in that order.

We could write an aggregate with positional association as follows:

(`f', `o', `o', `d') -- positional association

in which the elements are listed in the order of the index range, starting with the left bound of the range.

Alternatively, we could write an aggregate with named association:

( 3=> `f', 2=> `o', 0 => `d', 1=> `o') -- named association

In this case, the index for each element is explicitly given, so the elements can be in any order.

Positional and named association can be mixed within an aggregate, provided all the positional associations come first.

Also, the word others can be used in place of an index in a named association, indicating the default value to be used for all elements not explicitly mentioned.

For example, the same value as above could be written as:

( `f', 0 => `d', others => `o').


Records

VHDL provides basic facilities for records, which are collections of named elements of possibly different types.

When you need to refer to a field of a record object, you use a selected name.

Suppose that ireg is a record object containing a field called op_code.

As for arrays, aggregates can be used to write literal values for records.

Both positional and named association can be used, and the same rules apply, with record field names being used in place of array index names.


Array based attributes

For any array type or object A, and N an integer between 1 and the number of dimensions of A, the following attributes can be used:

attribute name prefix result
A'left(N)

A'right(N)

array returns the left bound of the Nth index range of A; N is of type universal integer; result type is of type of the left bound of the left index range; N=1 if omitted

the same as A'left(N) except that the right bound is returned

A'high(N)

A'low(N)

array returns the upper bound of the range of A; result type is the type of the Nth index range of A; N=1 if omitted

the same as A'high(N) except that the low bound is returned

A'range(N)

A'reverse_range(N)

array returns range of A'left(N) to A'right(N)

returns range of A'ight(N) to A'left(N)


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