Introduction

Digital logic designers face a difficult task. They must create designs consisting of tens-of-thousands of gates while meeting ever increasing pressure to shorten time-to-market. In addition, designers need to maintain technology independence, without sacrificing silicon efficiency.

Meeting these requirements with today's EDA technology is not easy. Schematic-based design entry, though providing superior efficiency, deals with low level functions that are technology dependent. High-level Design Languages (HDLs) offer technology independence, but not without a significant loss of silicon efficiency and performance.

Bridging this gap between technology-independence and efficiency was difficult because there has never been a standard set of functions that were supported by all EDA and IC vendors. This has now changed with the introduction of EDA tools that support the Library of Parameterized Modules (LPM).