Memory with a single I/O port.

Ports

Port Name	Type	Usage	Description	Comments
DIO	I/O	Required	bi-directional Data port	Vector, LPM_Width wide
Address	I	Required	Address of memory location	Vector, LPM_WidthAd wide
InClock	I	Note 1	Synchronous load of memory
OutClock	I	Note 2	Synchronous Q outputs from memory.
MemEnab	I	Optional	Memory Output Tristate Enable	Note 3
OutEnab	I	Optional	High (1): Memory[Address] to DIO Low (0): DIO to Memory[Address]	Note 4
WE	I	Required	Write enable control. Enables write to the memory when high (1).	Note 5

Note 1: If the InClock port is used, then the WE port acts as an enable for write operations synchronized to the positive going edge of the signal on the InClock port. If the InClock ports is not used, then the WE port acts as an enable for write operations asynchronously.

Note 2: The addressed memory content to Q response is synchronous when the OutClock port is connected. and asynchronous when it is not connected.

Note 3: When low, the memory is inactive and the outputs are Hi-Z. This also disables the ability to write to memory.

Note 4: Same as ~WE. Only one of OutEnab or WE should be used.

Note 5: Same as ~OutEnab. Only one of WE or OutEnab should be used. If no clock ports are used, when WE is active (high, 1) the data on the Address port should not change. If the data on the Address port changes while WE is high (1), then all memory locations that are addressed are over-written with Data.

Properties

Property	Usage	Value	Comments
LPM_Width	Required	LPM Value > 0	Width of input and output vectors.
LPM_WidthAd	Required	LPM Value > 0	Width of Address Port. Note 1.
LPM_NumWords	Optional	LPM Value > 0	Number of words stored in Memory. Note 2.
LPM_InData	Optional	REGISTERED | UNREGISTERED	Indicates if Data port is registered. Default is REGISTERED
LPM_Address_Control	Optional	REGISTERED | UNREGISTERED	Indicates if Address, MemEnab and WE ports are registered. Default is REGISTERED
LPM_OutData	Optional	REGISTERED | UNREGISTERED	Indicates if Q port is registered. Default is REGISTERED
LPM_File	Optional	File Name	File for RAM initialization.

Note 1: The LPM_WidthAd should be (but is not required to be) equal to: log₂(LPM_NumWords). If LPM_WidthAd is too small, some memory locations will not be addressable. If is too big, then the addresses that are too high will return UNDEFINED.

Note 2: If LPM_NumWords is not used, then it defaults to 2^LPM_WidthAd. In general, this value should be (but is not required to be): 2^{LPM_WidthAd-1} < LPM_NumWords < = 2^LPM_WidthAd.

Functions

Random Access Memory. This module can represent asynchronous memory or memory with synchronous inputs and/or outputs.

Synchronous Memory Operations

Synchronous Write to memory

InClock	Mem-Enab	WE or ~OutEnab	Memory contents
X	L	X	Hi-Z (memory not enabled)
rising edge	H	L	No change (no write enable)
not rising edge	H	H	No change (requires positive going clock edge)
rising edge	H	H	DIO to Memory[Address] controlled by WE

Synchronous Read from memory

OutClock	Mem-Enab	Out-Enab or ~WE	Output (Note 1)
X	L	X	Hi-Z (memory not enabled)
rising edge	H	L	DIO acts as an input to the LPM_RAM_IO.
rising edge	H	H	The output register is loaded with the contents of the memory location pointed to by Address. DIO outputs the contents of the output register. Note 1
not rising edge	H	H	No change. DIO is held constant until next clock. Data will change on next OutClock.

Note 1: WE does not act as a clock enable for the output clock.

Asynchronous Memory Operations

Totally asynchronous memory operations occur when neither InClock nor OutClock is connected.

Mem-Enab	WE or ~OutEnab	Memory Contents (Note 1)
L	X	Hi-Z (memory not enabled)
H	L	No change (No Write Enable)
H	H	The memory location pointed to by Address is loaded with Data on DIO. Note 2

Note 1: When neither InClock nor OutClock is connected, the output DIO is asynchronous and reflects the data in the memory to which Address points when DIO is acting as an output.

Note 2: The data on the Address port should not change while WE is high (OutEnab is low). If the data on the Address port changes while WE is high (OutEnab is low), then all memory locations that are addressed are over-written with DIO.