Ports

Port Name	Type	Usage	Description	Comments
DataA	I	Required	Multiplicand	Vector, LPM_WidthA wide
DataB	I	Required	Multiplier	Vector, LPM_WidthB wide
Sum	I	Optional	Partial Sum	Vector, LPM_WidthS wide. Note 1
Result	O	Required	Product	Vector, LPM_WidthP wide. Note 2
Clock	I	Optional	Clock for pipelined usage	Note 3
Aclr	I	Optional	Asynchronous Clear	Note 4

Note 1: An extra bit should be reserved in the LPM_WidthS if a carry out is expected from addition of the Product and the Partial Sum. LPM_WidthS should be larger than LPM_WidthA plus LPM_WidthB to guarantee that the carry out will be represented in Result.

Note 2: The product is a vector, LPM_WidthP bits wide. If LPM_WidthP is less than the maximum of either LPM_WidthA plus LPM_WidthB or LPM_WidthS, then only the LPM_WidthP most significant bits are present.

Note 3: The clock port provides for pipelined operation of the LPM_MULT. If a latency other 0 (default value) is specified, then the clock port must be connected.

Note 4: The pipelined initializes to undefined. The Aclr port may be used at any time to reset the pipeline to all 0's asynchronously to clock.

Properties

Property	Usage	Value	Comments
LPM_WidthA	Required	LPM Value > 0	Width of DataA
LPM_WidthB	Required	LPM Value > 0	Width of DataB
LPM_WidthS	Optional	LPM Value > 0	Width of Sum. Required if the Sum port is used.
LPM_WidthP	Required	LPM Value > 0	Width of Result. This represents the LPM_WidthP most significant bits.
LPM_Representation	Optional	UNSIGNED or SIGNED	Default is UNSIGNED.
LPM_Pipeline	Optional	LPM Value > = 0	Default is 0 - non-pipelined

Function

Result = (DataA * DataB) + Sum

The LSB of the product of DataA and DataB is aligned with the LSB of Sum.

Example

The partial product is represented by P, and the full product by X. Both are internal only.

Copyright © 1998 University of Manchester