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Synthesizing "+" : Part Two

Let’s carry on from where we left off last month. We saw that in order to compensate for the literal interpretation of the usual RTL synthesis rules by some synthesis tools, it was necessary to write the VHDL code for the desired hardware architecture. Such code tuning is often necessary for arithmetic circuit synthesis.

Now there are some synthesis tools that are able to infer the hardware architecture from the code functionality rather than from a set of syntactic rules. In this case, the code snippett

compare_add: process (a, b, c)
  variable s : std_logic_vector (7 downto 0);
begin
  if (a > b) then
    s := s + 1;
  end if;
  if (c = '1') then
    s := s + 1;
  end if;
  ...
end process;

becomes synthesised as:

Oh, jolly good! These are proper synthesis tools aren't they? Well, er, no, actually. You can see that in this architecture there are three arithmetic path delays from a, b to s. In the multiplexer-oriented structure, there are only two arithmetic path delays (the mux delays are often insignificant compared to arithmetic unit delays). And once again, you’re stuck with the initial architecture created by the RTL synthesis tool.

All RTL synthesis tools suffer the same underlying problem; a single hardware architecture derived from the RTL code.

Suppose we want a fast data path from the a, b inputs to the s output and an efficient architecture from any synthesis tool. To do this, the hardware architecture must be more explicitly coded in the VHDL:

  signal compare : std_logic;
  signal c2 : std_logic_vector (1 downto 0);
  signal s_in : std_logic_vector (7 downto 0);
  signal s : std_logic_vector (7 downto 0);

...

  fixed_compare : compare <= a > b;

  c2(1) <= compare and c;
  c2(0) <= compare xor c;

  fixed_adder: s <= s_in + c2;

The key feature of this code is that there is but one "+" operator. The conceptual adder for compare and c has been reduced to a half-adder coded as logical operators rather than using "+". For some synthesis tools, you may need to preserve the comparator derived from the ">" operator by preventing the compare signal from being optimized away through the use of a synthesis tool-specific command.

So the tips here are:

• Only use "+" where you really need an adder
• Write low-level code if you want firm control over the synthesised design.

Previous Tips of the Month can be downloaded from here...

Comprehensive VHDL for FPGA / ASIC
Advanced VHDL for Synthesis

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