Model of the Month

BIST Circuits, Part One

For the next two months, we are going to present a collection of circuits following the Built-in Self Test (BIST) theme. These circuits will enable you to incorporate BIST into your designs using the principles of signature analysis. At the heart of most designs using this BIST approach, lies a pseudo-random bit stream (PRBS) generator. The PRBS generator is most easily implemented using a linear feedback shift register (LFSR). The LFSR can be used to both generate the test sequence for the design that is to incorporate BIST and with slight modification can be used to capture the response of the design and generate a signature (the bit pattern held in the register). This signature is then compared to a known good signature. Within certain realms of mathematical probablity, if the signature for the circuit being tested is the same as the known good signature, then the tested circuit is deemed as being functionally correct. More on the maths later on...

First of all, though, let's build ourselves an LFSR. This first design is going to be a 10-bit design.

library IEEE;
use IEEE.std_logic_1164.all;

entity maximal_length_lfsr is
port (
  clock    : std_ulogic;
  reset    : std_ulogic;
  data_out : out std_ulogic_vector(9 downto 0)
);
end maximal_length_lfsr;

architecture modular of maximal_length_lfsr is

  signal lfsr_reg : std_ulogic_vector(9 downto 0);

    signal cycle : integer := -1;

begin

  process (clock)
    variable lfsr_tap : std_ulogic;
  begin
    if clock'EVENT and clock='1' then
      if reset = '1' then
        lfsr_reg <= (others => '1');
      else
        lfsr_tap := lfsr_reg(6) xor lfsr_reg(9);
        lfsr_reg <= lfsr_reg(8 downto 0) & lfsr_tap;
      end if;
    end if;
  end process;
  
  data_out <= lfsr_reg;
  
end modular;

Next, we have to come up with the signature register. This is a modified version of the LFSR, with an extra XOR gate on the data input to the LSB of the register.

library IEEE;
use IEEE.std_logic_1164.all;

entity signature_register is
port (
  data_in  : std_ulogic;
  clock    : std_ulogic;
  reset    : std_ulogic;
  data_out : out std_ulogic_vector(9 downto 0)
);
end signature_register;

architecture RTL of signature_register is

  signal lfsr_reg : std_ulogic_vector(9 downto 0);
  
begin

  process (clock)
    variable lfsr_tap : std_ulogic;
  begin
    if clock'EVENT and clock='1' then
      if reset = '1' then
        lfsr_reg <= (others => '0');
      else
        lfsr_tap := lfsr_reg(6) xor lfsr_reg(9);
        lfsr_reg <= lfsr_reg(8 downto 0) & (lfsr_tap xor data_in);
      end if;
    end if;
  end process;
  
  data_out <= lfsr_reg;

end RTL;

By combining these two design, a stand-alone generator and tester circuit can be created:

library IEEE;
use IEEE.std_logic_1164.all;

entity sisr is
port (
  serial_in     : std_ulogic;
  clock         : std_ulogic;
  reset         : std_ulogic;
  lfsr_out      : out std_ulogic_vector(9 downto 0);
  signature_out : out std_ulogic_vector(9 downto 0)
);
end sisr;

library DFT;

architecture modular of sisr is
  use DFT.all;
  
  -- signal
  component maximal_length_lfsr 
  port (
    clock    : std_ulogic;
    reset    : std_ulogic;
    data_out : out std_ulogic_vector(9 downto 0)
  );
  end component;
  
  component signature_register
  port (
    data_in  : std_ulogic;
    clock    : std_ulogic;
    reset    : std_ulogic;
    data_out : out std_ulogic_vector(9 downto 0)
  );
  end component;

begin

  generator: maximal_length_lfsr port map (clock, reset, lfsr_out);
  
  analyzer: signature_register port map (serial_in, clock, reset,
    signature_out);
  
end modular;

You are welcome to use the source code we provide but you must keep the copyright notice with the code (see the Acknowledgements page for more details).

The VFP Library is required for simulating this month's Model of the Month.
To download the VFP files, click here.

Here is a skeleton testbench architecture that can be used for testing designs. This particular testbench creates a 10-bit parallel data path for input to the faulty circuit and analyzes the single bit output from the faulty circuit.

architecture modular of sisr_tb is
  -- declarations
begin

  tester: sisr port map (serial_in, clock, reset, lfsr_out,
    parallel_out);
  
  dut: fault_circuit port map (lfsr_out, serial_in);
  
  -- testbench stimulus and respose-checking
  
end modular;

To download the VHDL source code for this month's
Model of the Month, click here.

VHDL source code for other Models of the Month
can be downloaded from here.