Model of the Month

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Simple RAM Model

Some of you asked for a VHDL version of the simple RAM model presented on December’s Model of the Month page, so here it is. Once again we can highlight the differences between Verilog and VHDL in modeling a design.

Conceptually, the RAM’s address is used as an index into the memory array provided in either language. In VHDL, this concept is strictly adhered to, in that the address is regarded as an integer from the memory array’s perspective. However, the address port is modelled as a std_logic_vector object. Type mismatch! Now, the same is true in Verilog, conceptually the address is an index into memory and the address port is modelled as a vector. Except that in Verilog, there is no concept of a type, hence in Verilog, the value on the address port is interpreted as an integer for memory indexing statements in the always block. In VHDL, such interpretation is forbidden. So, in VHDL code, it is necessary to use a type conversion function to allow a std_logic_vector value on the address port to be used as an integer index into the memory array. For code minimalists, Verilog 1 VHDL 0.

But...

This memory model uses a bidirectional port for the data bus. In Verilog, such an inout port must be driven by a wire object and must only drive a wire object. This means that although the RAM read and write operations are conveniently described in an always block, it is necessary to use a continuous assignment to “convert” the register assignment to data made in the always block to a wire assignment as required by Verilog’s inout assignment rules. In VHDL, there are no such inhomogeneities, a signal is a signal is a signal. In VHDL, it is a simple matter to use a single process. Verilog 1 VHDL 1.

To summarise the key code points from this RAM model, we have:

• Single process style
• std_logic_vector to integer conversion is required

You are welcome to use the source code we provide but you must keep the copyright notice with the code (see the Acknowledgements page for more details).

The VFP Library is required for simulating this month's Model of the Month.
To download the VFP files, click here.

-- Simple RAM Model
--
-- +-----------------------------+
-- |    Copyright 1997 DOULOS    |
-- |       Library: Memory       |
-- |   designer : John Aynsley   |
-- +-----------------------------+
 
-- Architectures:
--   03.02.97 Behaviour

library IEEE;
use IEEE.std_logic_1164.all;
use vfp.generic_conversions.all;

entity RamChip is
  port (Address: in Std_logic_vector(3 downto 0);
        Data: inout Std_logic_vector(7 downto 0);
        CS, WE, OE: in Std_logic);
end;

architecture Behaviour of RamChip is
begin
  process(Address, CS, WE, OE)
    subtype Byte is Std_logic_vector(7 downto 0);
    type Mem is array (0 to 15) of Byte;
    variable Memory: Mem := (others => Byte'(others=>'U'));
  begin
    Data <= (others => 'Z');
    if CS  = '0' then
      if OE = '0' then			-- Read operation
        Data <= Memory(To_Integer(Address));
      elsif WE = '0' then		-- Write operation
        Memory(To_Integer(Address)) := Data;
      end if;
    end if;
  end process;
end;

VHDL source code for other Models of the Month
can be downloaded from here.

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This page was last updated 24^th January 1997.

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