Model of the Month

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Analog-to-Digital Converter Model

The VHDL code presented in this month's Model of the Month will enable you to see how to create behavioural ADC models of a particular accuracy.

The example we present is for an 8-bit ADC, but you can easily modify the digital output wordlength for any desired accuracy of ADC.

The 8-bit ADC model is built around a function, ADC_8b_10v_bipolar. Just to make the code a little bit more interesting, there are conversion operators sprinkled throughout the VHDL code. Conversion operators are similar to conversion functions in that they perform the same functionality. In the case of conversion functions, we may write code like this:

a_vector := to_std_ulogic_vector (an_integer, num_bits_in_vector);

where to_std_ulogic_vector is a conversion function that takes an integer parameter and converts it to an object of std_ulogic_vector type.

For a conversion operator, we use VHDL’s operator overloading capability. This allows us to re-define the use of the equality operator so that instead of comparing two operands, the "=" operator examines the type of the left-hand operand and within the function defined for the overloaded "=" operator, converts the type of the right-hand operand to that of the left-hand operand.

The subtle aspect of this "=" operator overloading is that the operands are not of the same type, so there is no clash with the implicit "=" operators that VHDL creates for every type definition; in the implicit operators, the types of the operand are the same, of course.

You are welcome to use the source code we provide but you must keep the copyright notice with the code (see the Acknowledgements page for more details).

The VFP Library is required for simulating this month's Model of the Month
To download the VFP files, click here.

-- Analog-to-Digital Converter Model

-- +-----------------------------+
-- | Copyright 1995-1996 DOULOS  |
-- |      Library: analogue      |
-- |    designer : Tim Pagden    |
-- |     opened:  2 Feb 1996     |
-- +-----------------------------+

-- Architectures:
--   02.02.96 original
 
library ieee;
library vfp;
 
architecture original of ADC_8_bit is
  use ieee.std_logic_1164.all;
  use vfp.analog_class.all;
  use vfp.bus_class.all;
  use vfp.generic_conversions.all;
  use vfp.std_operators.all;
  use vfp.mixed_operators.all;
  use vfp.generic_functions.all;
  use vfp.twos_complement_types.all;
 
  constant conversion_time: time := 25 ns;

  signal instantly_digitized_signal : std_ulogic_vector(7 downto 0);
  signal delayed_digitized_signal : std_ulogic_vector(7 downto 0);
 
  function ADC_8b_10v_bipolar (
    analog_in: analog 
  ) return byte is
    constant max_abs_digital_value : integer := 128;
    constant max_in_signal : real := 10.0;
    variable digitized_2s_comp_signal : twos_complement(7 downto 0);
    variable analog_signal: real;  
    variable analog_abs: real;  
    variable analog_limited: real;  
    variable digitized_signal: integer;  
    variable digital_out: byte;  
  begin
    analog_signal := real(analog_in);
    if (analog_signal < 0.0) then    -- i/p = -ve
      digitized_signal := integer(analog_signal * 12.8);
      if (digitized_signal < -(max_abs_digital_value)) then
        digitized_signal := -(max_abs_digital_value);
      end if;
    else    -- i/p = +ve
      digitized_signal := integer(analog_signal * 12.8);
      if (digitized_signal > (max_abs_digital_value - 1)) then
        digitized_signal := max_abs_digital_value - 1;
      end if;
    end if; 
    digitized_2s_comp_signal := digitized_2s_comp_signal = digitized_signal;
    digital_out := byte(digitized_2s_comp_signal);
    return digital_out;
  end ADC_8b_10v_bipolar;
   
begin
 
  s0: instantly_digitized_signal <= 
        std_ulogic_vector (ADC_8b_10v_bipolar (analog_in));

  s1: delayed_digitized_signal <= 
        instantly_digitized_signal after conversion_time;

  s2: digital_out <= delayed_digitized_signal; 

end original;

To download the VHDL source code for this month's
Model of the Month, click here.

VHDL and Verilog source code for other Models of the Month
can be downloaded from here.

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This page was last updated 29^th March 1996.

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