-- +-----------------------------+
-- |    Copyright 1996 DOULOS    |
-- |     Library: arithmetic     |
-- |    designer : Tim Pagden    |
-- |     opened: 30 Jul 1996     |
-- +-----------------------------+

-- Architectures:
--   30.07.96 low_level

library arithmetic;
library multiplexer;

architecture low_level of scaler_4s_22s_negate_out is
  use multiplexer.mux_3_25_cmpt.all;
  use arithmetic.adder_25_cmpt.all;

  signal a_shift_3 : std_logic_vector(24 downto 0);
  signal a_shift_2 : std_logic_vector(24 downto 0);
  signal a_shift_1 : std_logic_vector(24 downto 0);
  signal a_pass    : std_logic_vector(24 downto 0);
  signal lo_25     : std_logic_vector(24 downto 0);

  signal sel_left  : std_logic_vector(1 downto 0);
  signal sel_right : std_logic_vector(1 downto 0);

  signal left_shift_in  : std_logic_vector(74 downto 0);
  signal right_shift_in : std_logic_vector(74 downto 0);

  signal left_shift_out  : std_logic_vector(24 downto 0);
  signal right_shift_out : std_logic_vector(24 downto 0);
  signal right_shift_xor : std_logic_vector(24 downto 0);

  signal subtract : std_logic;

begin

  sel_left_0: sel_left(0) <= b(2) xor b(1);

  sel_left_1: process (b(3 downto 1))
  begin
    if b(3) = '0' then
      sel_left(1) <= b(2) and b(1);
    else
      sel_left(1) <= b(2) nor b(1);
    end if;
  end process;

  sel_right_0: sel_right(0) <= b(0);
  sel_right_1: sel_right(1) <= (not b(0)) and b(1);

  a3: a_shift_3 <= a & "000";
  a2: a_shift_2 <= a(21) & a & "00";
  a1: a_shift_1 <= a(21) & a(21) & a & '0';
  ap: a_pass    <= a(21) & a(21) & a(21) & a;
  lo: lo_25     <= (others => '0');

  left_shift_in <= a_shift_3 & a_shift_2 & lo_25;
  right_shift_in <= a_shift_1 & a_pass & lo_25;

  subtract <= b(3) xor b(1);
  negate <= b(3);

  process (subtract, right_shift_out)
  begin
    if subtract = '0' then
      right_shift_xor <= right_shift_out;
    else
      right_shift_xor <= not right_shift_out;
    end if;
  end process;

  left_shifter: mux_3_25
  port map (
    a   => left_shift_in,
    sel => sel_left,
    y   => left_shift_out
  );

  right_shifter: mux_3_25
  port map (
    a   => right_shift_in,
    sel => sel_right,
    y   => right_shift_out
  );

  i0_0: adder_25
  port map (
    c_in  => subtract,
    a     => left_shift_out,
    b     => right_shift_xor,
    y     => y,
    c_out => open
  );

end low_level;