Writing Synthesisable Register Descriptions

Question: How do you know that your design will initialize properly when you simulate your register transfer level VHDL code prior to synthesis?

Answer: You don't! But you can help yourself uncover some of the problems by taking care to handle unknown logic values when writing the code...

Well, firstly let us not be guilty of finding a solution where there isn't a problem! Many of you will adopt a design methodology that ensures proper initialization every time, for example with an external asynchronous reset on every single flipflop and latch, in which case the following discussion may not be relevant. However, for the rest of you...

Consider what happens when you use an integer type. VHDL initializes integer signals to an explicit integer value of your choosing, or to 'LEFT by default, so the VHDL signal is guaranteed to initialize. However, synthesis will ignore such initial values, so the gate level implementation may not initialize at all! And your problems don't go away by using the types STD_LOGIC and STD_LOGIC_VECTOR, which have an explicit uninitialized value 'U', instead. Consider...

  F <= A when S = '0' else B;

Suppose that during initialization we have A = 'U', B = '1' and S = 'U'. Consider the equivalent hardware...

VHDL simulation sets F = '1', but gate level simulation has F = 'X', and in the silicon, F could have either logic level. So the VHDL simulation initializes fine, but after a possibly lengthy synthesis and gate level simulation run, you discover an initialization problem with the implementation!

The Cause: The VHDL conditional assignment is over optimistic. Any value other than '0' on S will cause the assignment F <= B, whether S = '1', 'H', 'L', 'U', 'X', 'W', '-' or 'Z' !

The Solution: We could try to catch the remaining values of S explicitly, something like...

  F <= 'X' when S = 'X' or S = 'U' else
     A  when S = '0' else
     B  when S = '1' else
     '-';

If we're lucky, this may work fine, because there are moves afoot in the synthesis community to treat comparison with unknown values as FALSE for synthesis (see the standard synthesis package IEEE Std 1076.3). However, currently some synthesis tools would throw out the S = 'X' as an error. We can make progress by re-ordering the comparisons as follows...

  F <= A when S = '0' else
    B when S = '1' else
    'X';

Now there is no explicit comparison with 'X', and some synthesis tools are happy because we have covered both the logical values for S with the first two branches, so the third branch assigning F <= 'X' will be ignored. This solution is a good compromise betweenaccuracy and simplicity. However, there are synthesis tools that would still throw out the 'X', so we must take an approach similar tothat given below, using synthesis directives to ignore the 'X'.

Now what happens if S = 'L' or 'H'? If we wanted to be fussy we could delve into the STD_LOGIC_1164 package and pull out the strength stripper function To_X01 and re-write the code thus...

  process (A, B, S)
    variable V: X01;
  begin
    V := To_X01(S);
    if V = '0' then
      F <= A;
    elsif V = '1' then
      F <= B;
      -- Whatever translate_off
    else
      F <= 'X';
      -- Whatever translate_on
    end if;
  end process;

The function To_X01 converts 'L' to '0', 'H' to '1', and all unknown values to 'X'. A process is used for efficiency to avoid calling To_X01 twice. This solution would be way over-the-top for most RTL simulation purposes, but will accurately model X propagation even if driven from nets with pullups or open collector outputs. The comments are directives to whatever synthesis tool to ignore the assignment F <= 'X'.

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