Simulation Ambiguities of VHDL

Question: Given the construct:

  wait until A'EVENT or B'EVENT;
  if A'EVENT then ...

When an event occurred on A, simulator X evaluated the if statement as TRUE, but simulator Y evaluated it as FALSE. Which is correct VHDL?

Answer: You have stumbled upon one of the few points in the VHDL language definition which can be interpreted in different ways. The LRM section in question is IEEE Std 1076-1987 page 8-2. paragraph 1, which states "If no sensitivity clause appears [ie. wait on ...], the sensitivity set will contain the signals denoted by the longest static prefix of each signal name that appears as a primary in the condition of the condition clause [ie. wait until ...]." In other words, if you omit the on part of a wait statement. the wait until condition will be evaluated when events occur on signals within that condition.

Unfortunately, as you have discovered, different VHDL tool developers have put different interpretations on this statement. The point in contention is whether the phrase "primary in the condition" should apply just to primaries at the first syntactic level within the condition (the primaries in your example are A'EVENT and B'EVENT, neither of which are themselves signals), or whether it should be applied recursively down inside the attributes (to include A and B in your example). Under the strict interpretation of the 1076 standard, the sensitivity set of your example is empty, so the wait statement never resumes, and simulator Y is correct!

As you would hope, the matter has been clarified in the VHDL 93 standard. The new LRM (page 112, lines 33-56) makes it clear that in your example the sensitivity set includes the signals A and B, so simulator X is correct!

If you were lost by all that VHDL mumbo jumbo, then do not despair! This is a pathological case that does not occur in normal healthy designs! The original example is perhaps better re-written...

  wait on A, B;

...which was probably the original intent anyway, that is wait until an event occurs on A or on B.

Another frequently seen example is:

  wait until Clock'EVENT and Clock = '1';

This will work on any current VHDL 87 simulator, because the appearance of Clock in the relation Clock = '1' causes the Clock signal to be put into the sensitivity set of the wait statement. The Clock'EVENT part is redundant! More elegant solutions are...

  wait until Clock = '1';
  wait until Rising_edge(Clock);

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