Integer Types and Subtypes

Question: When writing VHDL to synthesize a counter, I usually use an integer signal something like...

  signal Count: INTEGER range 0 to 7;

In examples of VHDL code in books I have seen...

  type Int is range 0 to 7;

used to define integers, without using the name INTEGER. What is the significance of using the name INTEGER within an integer sub-range, and is there any advantage in doing it the other way? Am I missing something?

Answer: You have touched on an area of VHDL that is often ignored or misunderstood. However, perhaps the first thing to say is that the style of code you are using is perfectly good, you have nothing to worry about, and you are not missing anything really important!

You have been making subtypes of the predefined type INTEGER, whereas the alternative (without the name INTEGER) is to create a totally new integer data type.

Consider the following VHDL...

  subtype One is INTEGER range 0 to 7;
  type Two is range 0 to 7;
  signal S1: One;
  signal S2: Two;
  signal S3: INTEGER;

Signals S1 and S2 both store integers in the range 0 to 7, but they are of different VHDL data types. Type One is a subtype of the type INTEGER (it uses the name INTEGER in its definition), and thus signal S1 is ultimately an INTEGER, whereas type Two is a completely new integer type. VHDL lets you both define new integer types (using the syntax given for Two), and create subtypes of existing types (using the syntax given for One).

Signal S3 is an INTEGER, and thus is of the same type as S1. The type INTEGER is an integer type that just happens to have been predefined in the package STD.STANDARD.

So what?

The difference between types and subtypes becomes apparent when you try using the signals. Consider the following VHDL...

  S1 <= S3;
  S2 <= S3;
  S2 <= Two(S3);

The first assignment S1 <= S3; may cause a run time error during simulation, because the values of S1 are constrained to the range 0 to 7. The second assignment S2 <= S3; is actually illegal VHDL, and will be rejected by the VHDL compiler, because S2 and S3 are of different data types! This is fixed in the third assignment S2 <= Two(S3); which uses the name of an integer type (Two) as a type conversion function between two integer types.

In summary, VHDL types get checked at compile time, whereas subtypes get checked at run time, during simulation. Choosing to use subtypes (as you originally did) makes the code easier to write, because you do not need to worry about type compatibility, but finding errors is dependent on the quality of the simulation test vectors. Choosing to use new integer types generally makes the VHDL more awkward to write, because you cannot mix different integer types without using explicit type conversions. The benefit is that certain classes of error can be caught by the VHDL compiler.

The VHDL type system exists so that you can express your design intent in such a way that the compiler can find a lot of the errors. Declaring a new integer type tells the compiler that you intend to manipulate a new class of integer that is not to be confused with (or mixed with) other integers. If this all seems rather over-the-top for a hardware description language, it is perhaps indicative of VHDL's roots in the ada software programming language.

Returning to the question, I would suggest that there is no reason to re-write your code to take advantage of integer types. However, there are some other important considerations regarding the use integer types to describe and synthesize counters. How are you going to check that the counter gets properly initialized? How can you describe counters more than 31 bits wide? How can you tap bits off from the middle of the counter? The answer to these questions is to abandon integer types altogether and use the type STD_LOGIC_VECTOR instead, but that is another story!

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