Using Aliases as a Coding Shortcut

Question: I've been writing some VHDL code to decode an address bus, which is defined in VHDL as a Std_logic_vector signal. For my application I'm only interested in decoding part of the bus - the high order bits. The code is as follows.

  signal address: std_logic_vector(15 downto 0);

  process (address(15 downto 12))
  begin
    case address(15 downto 12) is
    when "0000" =>
    -- etc
  end process;

Can I define a subtype of the bus, so that I do not have to keep repeating the range of bits that I'm decoding? I have tried the following, but it will not compile.

  subtype topbits is address(15 downto 12);

  process (topbits)
  begin
    case topbits is
    -- etc
  end process;

Answer: VHDL subtypes cannot be used in this way. Let's start by reviewing subtypes, and then show how you can solve the problem in another way!

Technically speaking, a subtype is defined by naming an existing type together with a constraint, for example:

  subtype topbits is std_logic_vector(15 downto 12);

Your subtype definition is not legal VHDL, because address is a signal, not a type. Also, the subtype itself cannot be used to store a value, which is what you have tried to do. But it could be used, for example, to declare a new signal as follows:

  signal tb: topbits;

Now we could use this new signal to store the top end of the address bus, as follows:

  tb <= address(15 downto 12);

  process (tb)
  begin
    case tb is
    -- etc
  end process;

This is legal VHDL, and will simulate and synthesize correctly. Mind you, this solution is not particularly elegant or efficient as we've had to define an extra signal and make a redundant signal assignment. Moreover, assigning a new value to tb will not change the value of address - the relationship between address and tb is unidirectional.

However, VHDL actually has another, ready-made solution up its sleeve - the alias. Aliases are a lesser known VHDL construct for doing exactly this sort of thing. The syntax is:

  signal address: std_logic_vector(15 downto 0);
  alias  topbits: std_logic_vector(3 downto 0) is address(15 downto 12);

  process (topbits))
  begin
    case topbits is
    when "0000" => 
    -- etc
  end process;

An alias is an alternative name for all or part of a signal, variable or constant. This is a much smarter solution that the previous one, because no new signals or variables need to be introduced. The alias topbits is just another name for the top bits of signal address. Moreover, when you define an alias you are free to choose a new range for addressing the bits of the vector (in this example, topbits(3) is an alias for address(15))

There is a catch. (There is always a catch.)

The catch is that although aliases are kosher, 100% legal IEEE Std 1076 VHDL, they are not supported by all VHDL synthesis tools. So if your synthesis tool does not support aliases, you would have to use the first solution.

By the way, in VHDL 93 the idea of an alias has been extended such that it can be an alternative name for almost anything in VHDL.

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