--
-- Rcsid[] = "$Id: stater.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

entity stater is
port(W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,RESETOUT: out bit;
     HLDA,HLTA,READY,VINT,CLK,RESETIN,GND,VCC,CC6,BIMC,M1: in bit);
end;

architecture structure of stater is

component DECOD3_8
port(A: in bit_vector(2 downto 0);
	 ENABLE_N: in bit;
	 Y: out bit_vector(7 downto 0));
end component;

component SN85150
port(out_z: out bit;
	 e0, e1, e2, e3, e4, e5, e6, e7: in bit;
	 e8, e9: in bit;
	STATE: in bit_vector(3 downto 0));
end component;

signal im1, iclk: bit;
signal ihalt, u33, u34, u22, u08, u38, u3A, u0A: bit;
signal zz0, zz1, zz2, zz3: bit;
signal ivint, icc6, iready : bit;
signal ww3, ww2, ww1, ww0: bit;
signal z: bit_vector(3 downto 0);
signal z0bar, zz0bar, zzreset, reset: bit;
signal FF_OUT, ZZRESETOUT : bit;

begin
INV0  : inv_gate generic map (1,1) port map (ivint,VINT);
INV1  : inv_gate generic map (1,1) port map (icc6,CC6);
INV2  : inv_gate generic map (1,1) port map (ihalt,HLTA);
INV3  : inv_gate generic map (1,1) port map (im1,M1);
INV4  : inv_gate generic map (1,1) port map (iready,READY);
INV5  : inv_gate generic map (1,1) port map (iclk,CLK);
and0  : AND_gate generic map (2,2) port map (u33,im1,HLDA);
and1  : AND_gate generic map (2,2) port map (u34,icc6,HLDA);
u0    : NOR_gate generic map (1,1) port map (u22,BIMC,READY);
u1    : OR_gate generic map (2,2) port map (u08,VINT,HLDA);
u2    : OR_gate generic map (2,2) port map (u38,HLDA,ivint);
u3    : OR_gate generic map (2,2) port map (u3A,HLDA,HLTA);
u4    : OR_gate generic map (2,2) port map (u0A,HLDA,ihalt);
--
-- TSTATES state machine
-- The next four components, the sn85150's, select the next state.
-- The four DFF1's contain the current TSTATE value.
--
COMP3 : SN85150 port map(ww3,GND,HLTA, GND,u33,u34,GND,HLDA,GND,   u38, u3A,z(3 downto 0));
COMP2 : SN85150 port map(ww2,GND, GND, u22, M1,CC6,VCC,GND, iready,GND, GND,z(3 downto 0));
COMP1 : SN85150 port map(ww1,GND,ihalt,VCC,GND,GND,VCC,GND, VCC,   GND, GND,z(3 downto 0));
COMP0 : SN85150 port map(ww0,VCC, GND, VCC,im1,VCC,GND,VCC, VCC,   u08, u0A,z(3 downto 0));
DF_0   : DFF1     port map(zz0,ww0,CLK,VCC,reset);
DF_0_A : inv_gate port map(zz0bar,zz0);
DF_1   : DFF1     port map(zz1,ww1,CLK,VCC,reset);
DF_2   : DFF1     port map(zz2,ww2,CLK,VCC,reset);
DF_3   : DFF1     port map(zz3,ww3,CLK,VCC,reset);
--
COMP4 : DECOD3_8 port map(z(2 downto 0),z(3),W7,W6,W5,W4,W3,W2,W1,W0);
and2  : NAND_gate generic map (1,1) port map (W8,z(3),z0bar);
and3  : NAND_gate generic map (1,1) port map (W9,z(3),z(0));
--and3  : INV_gate generic map (1,1) port map (W9,z(3));
RESETINFF  : DFF1  port map(zzreset,VCC,CLK,VCC,RESETIN);
RESETOUTFF : DFF1  port map(FF_OUT, VCC,iclk,VCC,reset);
OUTFF_A : inv_gate port map(ZZRESETOUT,FF_OUT);
BUF1 : BUF_gate generic map (2,2) port map (z(0),zz0);
BUF2 : BUF_gate generic map (2,2) port map (z0bar,zz0bar);
BUF3 : BUF_gate generic map (2,2) port map (z(1),zz1);
BUF4 : BUF_gate generic map (2,2) port map (z(2),zz2);
BUF5 : BUF_gate generic map (1,1) port map (z(3),zz3);
BUF6 : BUF_gate generic map (2,2) port map (reset,zzreset);
BUF7 : BUF_gate generic map (2,2) port map (RESETOUT,ZZRESETOUT);
end structure;

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