--
-- Rcsid[] = "$Id: sp_cntrl.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

entity sp_cntrl is
port(INCRLATCH,DECRLATCH,SPOUT,LOADLATCH,RETRN: out bit;
  ID0,ID1,ID4,ID5,ID7,ID9,ID19, CALL,XTHL,CCBAR,
  M1,M2,M3,M4, T1,T2,T3,T4,T5,T6, LASTMT,I3: in bit);
end;

architecture structure of sp_cntrl is

signal RST, PUSH, POP, RET, RET_COND, n6, n7, n9: bit;
signal n10, n11, n12, n13, n14, n15, n16, n17 : bit;
signal n20, n21, n22, n25, n26: bit;
signal n30, n31, n32, n33, n36: bit;
signal M1T5,M1T6,M2T2,M3T3,M4T1: bit;
signal n33a,n33d,n36a: bit;
signal CALLCOND,RETRN_buf: bit;

begin
u0a : or_gate generic map (1,1) port map(CALLCOND,ID19,ID4,CCBAR);
U1 : or_gate generic map (1,1) port map(RST,ID7,ID19);
U2 : or_gate generic map (1,1) port map(PUSH,ID19,ID5,I3);
U3 : or_gate generic map (1,1) port map(POP,ID19,ID1,I3);
U4 : or_gate generic map (1,1) port map(RET,ID19,ID1,ID9);
U5 : or_gate generic map (1,1) port map(RET_COND,CCBAR,ID19,ID0);
U6 : and_gate generic map (1,1) port map(n6,CALL,CALLCOND);
U7 : and_gate generic map (1,1) port map(n7,RST,PUSH);
U9 : nor_gate generic map (1,1) port map(n9,XTHL,M4,T2);
U10 : and_gate generic map (1,1) port map(n10,n11,XTHL);
U11 : and_gate generic map (1,1) port map(n11,POP,RET,RET_COND);
U12 : nor_gate generic map (1,1) port map(n12,n6,M4,T2);
U13 : nor_gate generic map (1,1) port map(n13,M1T5,n6);
U14 : nor_gate generic map (1,1) port map(n14,M1T5,n7);
U15 : nor_gate generic map (1,1) port map(n15,n7,M2T2);
U16 : nor_gate generic map (1,1) port map(n16,n10,M2T2);
U17 : nor_gate generic map (1,1) port map(n17,n11,M3,T2);
U18 : or_gate generic map (1,1) port map(DECRLATCH,n12,n13,n14,n15,n9);
U19 : or_gate generic map (1,1) port map(INCRLATCH,n16,n17);
U20 : and_gate generic map (1,1) port map(n20,XTHL,n6);
U21 : nor_gate generic map (1,1) port map(n21,M4,T3,n20);
U22 : nor_gate generic map (1,1) port map(n22,XTHL,M3T3);
U25 : and_gate generic map (1,1) port map(n25,n7,n10);
U26 : nor_gate generic map (1,1) port map(n26,n25,M2,T3);
U29 : or_gate generic map (1,1) port map(SPOUT,n21,n22,n26,n32,n33d);
U30 : nor_gate generic map (1,1) port map(n30,n36,n25); -- load PC in latch
U31 : and_gate generic map (1,1) port map(n31,n25,n6); --  load SP in latch
U32 : nor_gate generic map (1,1) port map(n32,M1,T4,n31);
U33 : nor_gate generic map (1,1) port map(n33,n33a,n6); -- load PC back in latch
U33a : AND_gate port map(n33a,M1T6,M4T1);
U33d : nor_gate generic map (1,1) port map(n33d,M4,T1,n6); -- load SP into 16bit counter
                                  -- for CALL
U35 : or_gate generic map (1,1) port map(LOADLATCH,n32,n30,n33,n36a);
U36 : NAND_gate generic map (1,1) port map(n36,LASTMT,RETRN_buf);
U36a : NOR_gate generic map (1,1) port map(n36a,RETRN_buf,M1,T1);

-- FOR BRINGING OUT A SIGNAL FOR 'RETURN' INSTRUCTION
U37 : and_gate generic map (1,1) port map(RETRN_buf,RET,RET_COND);
U37a : buf_gate port map (RETRN,RETRN_buf);
U38 : OR_gate port map(M1T5,M1,T5);
u39 : OR_gate port map(M1T6,M1,T6);
U40 : OR_gate generic map (1,1) port map(M2T2,M2,T2);
U41 : OR_gate port map(M3T3,M3,T3);
U42 : OR_gate port map(M4T1,M4,T1);
end structure;

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