--
-- Rcsid[] = "$Id: shflogic.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

entity shflogic is
port(CARRYOUT: out bit;
     BO: out bit_vector(7 downto 0);
     ALU: in bit_vector(7 downto 0);
     CNPLUS4BAR,I3,I4,I5,ID7,ID16,ID15,ALUOUTEN,CARRYIN: in bit);
end;

architecture structure of shflogic is

component mux_4bit
port(Y: out bit_vector(0 to 3);
     A,B: in bit_vector(0 to 3);
     choose: in bit);
end component;

component ocnand
port(O: out bit_vector(7 downto 0);
     I: in bit_vector(7 downto 0);
     ENABLE: in bit);
end component;

component mux2to1
port (Z  : out bit;
      SEL,D0,D1 : in bit);
end component;

signal n14, n16, n17, n18, n19: bit;
signal n20, n25 : bit;
signal y0,y1,y2,y3: bit_vector(3 downto 0);
signal lshift, rshift, CMC, CNPLUS4: bit;

begin

U0: mux_4bit port map(y0(3 downto 0),ALU(7 downto 4),rshift,ALU(7 downto 5),n18);
U1: mux_4bit port map(y1(3 downto 0),ALU(3 downto 0),ALU(4 downto 1),n18);
U2: mux_4bit port map(y2(3 downto 0),y0(3 downto 0),y0(2 downto 0),y1(3),n19);
U3: mux_4bit port map(y3(3 downto 0),y1(3 downto 0),y1(2 downto 0),lshift,n19);

U4 : OCNAND port map(BO(7 downto 0),y2(3 downto 0),y3(3 downto 0),ALUOUTEN);
U5 : inv_gate generic map(1,1) port map(CNPLUS4,CNPLUS4BAR);
U6 : mux2to1 port map(rshift,I4,ALU(0),CARRYIN);
U9 : mux2to1 port map(lshift,I4,ALU(7),CARRYIN);
U14 : mux2to1 port map(n14,n20,CNPLUS4,n16);
U16 : mux2to1 port map(n16,I3,ALU(7),ALU(0));

U17 : inv_gate generic map(1,1) port map(n17,I3);
U18 : and_gate generic map(1,1) port map(n18,I3, n20);    -- rotate right
U19 : and_gate generic map(1,1) port map(n19,n17,n20);    -- rotate left
U20 : nor_gate generic map(1,1) port map(n20,I5,n25);     -- rotate

U25 : OR_gate generic map(1,1) port map(n25,ID16,ID7);
U26 : nor_gate generic map(1,1) port map(CMC,n25,ID15);  -- M1,T4
U28 : xor_gate generic map(1,1) port map(CARRYOUT,n14,CMC);
end structure;

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