--
-- Rcsid[] = "$Id: regpairs.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

entity regpairs is
port(
	Q: out bit_vector(0 to 15);
	D: in  bit_vector(0 to 15);
    CLEAR,VCC,WRLOW,WRHIGH,WRBOTH,CK: in bit
	);
end;

architecture structure of regpairs is

component reg8bits
port(Q: out bit_vector(0 to 7);
	 D: in bit_vector(0 to 7);
     CK, WRENABLE, CLEAR, PRESET: in bit);
end component ;

signal wrenable0, wrenable1: bit;

begin
U0 : reg8bits port map(Q(0 to 7),D(0 to 7),CK,wrenable0,CLEAR,VCC);
U1 : reg8bits port map(Q(8 to 15),D(8 to 15),CK,wrenable1,CLEAR,VCC);
U2 : or_gate generic map(1,1) port map(wrenable0,WRLOW,WRBOTH);
U3 : or_gate generic map(1,1) port map(wrenable1,WRHIGH,WRBOTH);
end structure;

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