--
-- Rcsid[] = "$Id: regctrl2.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

entity regctrl2 is
port(B_OUT,C_OUT,D_OUT,E_OUT,H_OUT,L_OUT,A_OUT,
     WRB,WRC,WRD,WRE,WRH,WRL,WRACC: out bit;
     M1,M2,T1,T3,T4,ID4,ID5,ID6,ID14,ID16,ID17,I0,I1,I2,
     I3,I4,I5,VCC,GND: in bit);
end;

architecture structure of regctrl2 is

component DECOD3_8
port(A: in bit_vector(2 downto 0);
     ENABLE_N: in bit;
     Y: out bit_vector(7 downto 0));
end component;

component mux_4bit
port(Y: out bit_vector(0 to 3);
     A,B: in bit_vector(0 to 3);
     choose: in bit);
end component;

signal n0, n1, n2, n3, n6, n7, n8, n9, n12: bit;
signal ns0, ns1, ns2, ns3, ns4, ns5, ns7: bit;
signal nd0, nd1, nd2, nd3, nd4, nd5, nd7: bit;
signal em0, em1, em2: bit;
signal SRCSEL, DSTSEL: bit;
signal n9a,n9b: bit;

begin
U0 : inv_gate generic map(1,1) port map(n0,ID14); -- not(INRM/DCRM)
U1 : and_gate generic map(1,1) port map(n1,ID16,ID17);
U2 : and_gate generic map(1,1) port map(n2,ID4,ID5);
U3 : inv_gate generic map(1,1) port map(n3,ID6);
U6 : or_gate generic map(1,1) port map(n6,M2,ID6,n1,T3);
U7 : or_gate generic map(1,1) port map(n7,ID16,n0,n2); -- INR/DCR
U8 : or_gate generic map(1,1) port map(n8,n3,M1,ID17,T4);
U9 : and_gate generic map(1,1) port map(n9,n9a,n7);
U9a : OR_gate generic map(1,1) port map(n9a,ID17,n9b); -- MOV r1,r2 / MOV M,r
U9b : INV_gate generic map(1,1) port map(n9b,ID6);
U10 : or_gate generic map(1,1) port map(SRCSEL,n9,M1,T4);
U11 : and_gate generic map(1,1) port map(DSTSEL,n6,n12,n8);
U12 : or_gate generic map(1,1) port map(n12,n7,M1,T1);
SRC_DECODER : DECOD3_8 port map(em2,em1,em0,SRCSEL,ns7,OPEN,ns5,ns4,ns3,ns2,ns1,ns0);
DST_DECODER : DECOD3_8 port map(I5, I4, I3, DSTSEL,nd7,OPEN,nd5,nd4,nd3,nd2,nd1,nd0);
INRDCRMUX :   mux_4bit port map(em0,em1,em2,OPEN,I3,I4,I5,GND,I0,I1,I2,GND,n7);
U14 : inv_gate generic map(1,1) port map(B_OUT,ns0);
U15 : inv_gate generic map(1,1) port map(C_OUT,ns1);
U16 : inv_gate generic map(1,1) port map(D_OUT,ns2);
U17 : inv_gate generic map(1,1) port map(E_OUT,ns3);
U18 : inv_gate generic map(1,1) port map(H_OUT,ns4);
U19 : inv_gate generic map(1,1) port map(L_OUT,ns5);
U20 : inv_gate generic map(1,1) port map(A_OUT,ns7);
U21 : inv_gate generic map(1,1) port map(WRB,nd0);
U22 : inv_gate generic map(1,1) port map(WRC,nd1);
U23 : inv_gate generic map(1,1) port map(WRD,nd2);
U24 : inv_gate generic map(1,1) port map(WRE,nd3);
U25 : inv_gate generic map(1,1) port map(WRH,nd4);
U26 : inv_gate generic map(1,1) port map(WRL,nd5);
U27 : inv_gate generic map(1,1) port map(WRACC,nd7);
end structure;

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