--
-- Rcsid[] = "$Id: reg8bits.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- This component is used to define some of the registers
-- and buffers in the 8085.  The clock is not gated, so
-- multiplexers are used to clock current register contents
-- back into DFFs if new values are not to be loaded.
   
entity reg8bits is
port(Q: out bit_vector(0 to 7);
	 D: in bit_vector(0 to 7);
     CK, WRENABLE, CLEAR, PRESET: in bit);
end;

architecture structure of reg8bits is

component buf8
port(BUF_OUT: out bit_vector(7 downto 0);
	 BUF_IN:  in  bit_vector(7 downto 0));
end component;

signal L, reg_in: bit_vector(0 to 7);

begin
R0  : DFF1 port map(L(0), reg_in(0),CK,PRESET,CLEAR);
R1  : DFF1 port map(L(1), reg_in(1),CK,PRESET,CLEAR); 
R2  : DFF1 port map(L(2), reg_in(2),CK,PRESET,CLEAR);
R3  : DFF1 port map(L(3), reg_in(3),CK,PRESET,CLEAR);
R4  : DFF1 port map(L(4), reg_in(4),CK,PRESET,CLEAR);
R5  : DFF1 port map(L(5), reg_in(5),CK,PRESET,CLEAR);
R6  : DFF1 port map(L(6), reg_in(6),CK,PRESET,CLEAR);
R7  : DFF1 port map(L(7), reg_in(7),CK,PRESET,CLEAR);
U9  : buf8 port map(Q(0 to 7), L(0 to 7));
U20 : mux2to1 port map(reg_in(0),wrenable,L(0),D(0));
U21 : mux2to1 port map(reg_in(1),wrenable,L(1),D(1));
U22 : mux2to1 port map(reg_in(2),wrenable,L(2),D(2));
U23 : mux2to1 port map(reg_in(3),wrenable,L(3),D(3));
U24 : mux2to1 port map(reg_in(4),wrenable,L(4),D(4));
U25 : mux2to1 port map(reg_in(5),wrenable,L(5),D(5));
U26 : mux2to1 port map(reg_in(6),wrenable,L(6),D(6));
U27 : mux2to1 port map(reg_in(7),wrenable,L(7),D(7));
end structure;

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