--
-- Rcsid[] = "$Id: intrupt2.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- This module is used to recognize a pending interrupt in the
-- last machine cycle of the instruction. It then generates INTA
-- and INA signals. It is also used to reset the RST 7.5 and
-- TRAP flipflops in interrupt1 module.
 
entity intrupt2 is
port(
     ACK2,ACK1,ACK0,INTRACK,RESETTRAP,INA,INTA,RESETRST75 : out bit;
     PRIENCODE: in bit_vector(2 downto 0);
     RESET,CK,EI,THALT,THOLD,T5,T3,T2,M1,LASTMCCYCLE,CC6,VCC: in bit
    );
end;

architecture structure of intrupt2 is

signal n0, n1, n2, n3, n4, n5, n6, n7, n8, n9: bit;
signal n10, n11, n14, n15, n16, n17: bit;
signal n21, n22, n23, n24: bit;
signal L1, L2, L3, L4, L5, L6, L7, L8: bit;
signal ACK2_buf,ACK1_buf,ACK0_buf: bit;

begin
U0  : DFF1 port map(L1,PRIENCODE(0),n3,RESET,VCC);
U1  : DFF1 port map(L3,PRIENCODE(1),n3,RESET,VCC);
U2  : DFF1 port map(L5,PRIENCODE(2),n3,RESET,VCC);
U0a : inv_gate port map(L2,L1);
U1a : inv_gate port map(L4,L3);
U2a : inv_gate port map(L6,L5);
U3  : and_gate generic map(1,1) port map(n3,CK,n4);
U4  : or_gate generic map(1,1) port map(n4,n7,n5);
U5  : and_gate generic map(1,1) port map(n5,EI,n6);
U6  : nand_gate generic map(1,1) port map(n6,THOLD,THALT);
U7  : nor_gate generic map(1,1) port map(n7,LASTMCCYCLE,n8);
U8  : and_gate generic map(1,1) port map(n8,n9,n10);
U9  : or_gate generic map(1,1) port map(n9,T2,n11);
U10 : or_gate generic map(1,1) port map(n10,M1,n24);
U11 : inv_gate generic map(1,1) port map(n11,M1);
U12 : and_gate generic map(1,1) port map(INTRACK,ACK0_buf,ACK1_buf,ACK2_buf);
U13 : nand_gate generic map(1,1) port map(RESETTRAP,n0,n1,n2);
U14 : nand_gate generic map(1,1) port map(n14,ACK0_buf,ACK1_buf);
U15 : and_gate generic map(1,1) port map(n15,n0,n1,ACK2_buf);
U16 : and_gate generic map(1,1) port map(n16,n14,n17);
U17 : inv_gate generic map(1,1) port map(n17,n15);
U18 : DFF1 port map(L7,n16,CK,VCC,RESET);
U19 : DFF1 port map(L8,n15,CK,VCC,RESET);
U20 : nand_gate generic map(1,1) port map(RESETRST75,ACK0_buf,n1,n2);
U21 : inv_gate generic map(1,1) port map(n21,CC6);
U22 : or_gate generic map(1,1) port map(n22,T5,n21);
U23 : or_gate generic map(1,1) port map(n23,T3,CC6);
U24 : and_gate generic map(1,1) port map(n24,n22,n23);

U30 : buf_gate generic map(2,2) port map(ACK0_buf,L1);
U30a : buf_gate port map (ACK0,ACK0_buf);
U31 : buf_gate generic map(2,2) port map(n0,L2);
U32 : buf_gate generic map(2,2) port map(ACK1_buf,L3);
U32a : buf_gate port map (ACK1,ACK1_buf);
U33 : buf_gate generic map(2,2) port map(n1,L4);
U34 : buf_gate generic map(2,2) port map(ACK2_buf,L5);
U34a : buf_gate port map (ACK2,ACK2_buf);
U35 : buf_gate generic map(2,2) port map(n2,L6);
U36 : buf_gate generic map(2,2) port map(INA,L7);
U37 : buf_gate generic map(2,2) port map(INTA,L8);
end structure;

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