--
-- Rcsid[] = "$Id: interupt.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- This module contains interrupt1, interrupt2, interrupt3 and vector_gen
-- as components.  It also generates VINT signal for the stater.

-- B16BOx stands for 16bit bus output ,and BUSOUTx for 8 bit bus o/p

entity interupt is
port(B16BO : out bit_vector(0 to 15);
     BUSOUT: out bit_vector(0 to 7);
     BUSIN6,BUSIN7: in bit;
	 BUSIN: in bit_vector(0 to 4);
     INA,SOD,INTA,VINT: out bit;
     TRAP,RST75,RST65,RST55,INTR,RESET,CK,ID19,ID16,ID14,ID12,ID3,ID0,
     THALT,THOLD,T5,T4,T3,T2,CC6,LASTMCCYCLE,CKBAR,SID,I5,I4,I3,M3,M1,RSTN,
     VCC,GND: in bit);
end;

architecture structure of interupt is
component intrupt1
port(PRIENCODE: out bit_vector(2 downto 0);
     EI,MASK75SET,MASK65SET,MASK55SET,RST75SET: out bit;
     TRAP,RST75,RST65,RST55,INTR,RESETTRAP,RESETRST75,RESET,CK,SIM: in bit;
     BUSIN: in bit_vector(0 to 4);
	 ID19,ID14,ID12,ID3,M1,T4,T2,INTACK,VCC: in bit);
end component;

component intrupt2
port(ACK2,ACK1,ACK0,INTRACK,RESETTRAP,INA,INTA,RESETRST75 : out bit;
     PRIENCODE: in bit_vector(2 downto 0);
     RESET,CK,EI,THALT,THOLD,T5,T3,T2,M1,LASTMCCYCLE,CC6,VCC: in bit);
end component;

component intrupt3
port(BUSOUT: out bit_vector(0 to 7);
    SOD,SIM: out bit;
    ACK: in bit_vector(2 downto 0);
    CK,CKBAR,M1,T3,T2,ID16,ID14,ID12,ID0,MASK75SET,MASK65SET,
    MASK55SET,RST55,RST65,RST75SET,SID,RESET,EI,BUSIN6,BUSIN7,VCC: in bit);
end component;

component vectrgen
port(B16O: out bit_vector(0 to 7);
     INA, RSTN, M3, T2, ACK1, ACK0, I5, I4, I3,GND,VCC: in bit);
end component;

signal PRIENCODE: bit_vector(2 downto 0);
signal EI, MASK75SET, MASK65SET, MASK55SET, RST75SET: bit;
signal RESETTRAP, RESETRST75: bit;
signal SIM, INTACK :bit;
signal ACK: bit_vector(2 downto 0);
signal INA_buf, INTA_buf: bit;

begin
F0 : INTRUPT1 port map(PRIENCODE(2 downto 0),EI,MASK75SET,
      MASK65SET,MASK55SET,RST75SET,TRAP,RST75,RST65,RST55,INTR,
      RESETTRAP,RESETRST75,RESET,CK,SIM,BUSIN(0 to 4),
      ID19,ID14,ID12,ID3,M1,T4,T2,INTACK,VCC);

F1 : INTRUPT2  port map(ACK(2 downto 0),INTACK,RESETTRAP,INA_buf,INTA_buf,
      RESETRST75,PRIENCODE(2 downto 0),RESET,CK,EI,
      THALT,THOLD,T5,T3,T2,M1,LASTMCCYCLE,CC6,VCC);

F2 : INTRUPT3 port map(BUSOUT(0 to 7),
      SOD,SIM,ACK(2 downto 0),CK,CKBAR,M1,T3,T2,
      ID16,ID14,ID12,ID0,MASK75SET,MASK65SET,MASK55SET,RST55,
      RST65,RST75SET,SID,RESET,EI,BUSIN6,BUSIN7,VCC);

F3 : or_gate generic map (1,1) port map(VINT,INA_buf,INTA_buf);

F4 : VECTRGEN  port map(B16BO(0 to 7),INA_buf,RSTN,M3,T2,ACK(1),ACK(0),I5,I4,I3,GND,VCC);
buf1 : buf_gate port map (INA,INA_buf);
buf2 : buf_gate port map (INTA,INTA_buf);
end structure;

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