--
-- Rcsid[] = "$Id: inst_reg.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- The new instruction gets clocked into Instruction register
-- in every M1(except INA) at the end of state T3.

entity inst_reg is
port(I: out bit_vector(5 downto 0);
     ID: out bit_vector(19 downto 0);
     BIN: in bit_vector(7 downto 0);
     INA,RESET,M1,T3,CLK, GND: in bit);
end;

architecture structure of inst_reg is

--component reg_8bit
--port(Q: out bit_vector(0 to 7);
--     D: in bit_vector(0 to 7);
--     CK, WRENABLE, CLEAR, PRESET: in bit);
--end component;

component DECOD3_8
port( A: in bit_vector(2 downto 0);
	  ENABLE_N: in bit;
	  Y: out bit_vector(7 downto 0));
end component;

signal CLOCK, PRESET: bit;
signal I6bar,I7bar: bit;
signal I_: bit_vector(7 downto 0);

begin
B8 : REG_8BIT port map(I_(7 downto 0),BIN(7 downto 0),CLK,CLOCK,RESET,PRESET);
NR : nor_gate generic map(1,1) port map(CLOCK,M1,T3,CLK);
--NR : INV_gate generic map(1,1) port map(CLOCK,CLK);
IV : inv_gate generic map(1,1) port map(PRESET,INA);

b1 : inv_gate generic map (1,1) port map(I6bar,I_(6));
b2 : inv_gate generic map (1,1) port map(I7bar,I_(7));
b3 : or_gate generic map (2,2) port map(ID(16),I_(6),I_(7));
b4 : or_gate generic map (2,2) port map(ID(17),I_(7),I6bar);
b5 : or_gate generic map (2,2) port map(ID(18),I_(6),I7bar);
b6 : or_gate generic map (2,2) port map(ID(19),I6bar,I7bar);

DCD0 : DECOD3_8 port map(I_(2 downto 0),GND,ID(7 downto 0));
DCD1 : DECOD3_8 port map(I_(5 downto 3),GND,ID(15 downto 8));

buf0 : buf_gate port map(I(0),I_(0));
buf1 : buf_gate port map(I(1),I_(1));
buf2 : buf_gate port map(I(2),I_(2));
buf3 : buf_gate port map(I(3),I_(3));
buf4 : buf_gate port map(I(4),I_(4));
buf5 : buf_gate port map(I(5),I_(5));
--buf6 : buf_gate port map(I(6),I_(6));
--buf7 : buf_gate port map(I(7),I_(7));

end structure;

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