-- -- Rcsid[] = "$Id: gl85.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $"; -- entity gl85 is port(CLK : in bit; RESETOUT, SOD: out bit; SID, TRAP, RST75, RST65, RST55, INTR: in bit; INTABAR: out bit; A15,A14,A13,A12,A11,A10,A9,A8: out bit; AD7,AD6,AD5,AD4,AD3,AD2,AD1,AD0: out bit; S0, ALE, WRBAR, RDBAR, S1, IOMBAR: out bit; READY, RESETINBAR: in bit; CLKOUT, HLDA: out bit; HOLD : in bit; DIN : in bit_vector(7 downto 0); VCC,GND: in bit); end; architecture structure of gl85 is signal ID: bit_vector(19 downto 0); signal I0,I1,I2,I3,I4,I5: bit; signal B8BO, B8BIN: bit_vector(0 to 7); signal B16BO, B16BIN: bit_vector(0 to 15); signal T1, T2, T3, T4, T5, T6: bit; signal ACCOUTEN, WRACC, WR2TEMP, WRAUXACC, ENBUSTOAUX: bit; signal INA, LASTMC, CC6, CCBAR: bit; signal RSTN, INTA, VINT, THALT, THOLD, TWAIT : bit; signal M1, M2, M3, M4, M5: bit; signal MDROUT, BIMC, ALUOUTEN, CC: bit; signal CLKOUT_buf,TEMP_OUT: bit; signal SEL16BUS,SEL_CNTR: bit; signal WRB,WRC,WRBC,WRPCH,WRPCL,WRPC: bit; signal BOUT,COUT,BCOUT,PCHOUT,PCLOUT,PCOUT,WRH,WRL,WRHL, WRD,WRE,WRDE,HOUT,LOUT,HLOUT,DOUT,EOUT,DEOUT: bit; signal SPOUT,WRSP,LOADLATCH,ENLATCHOUT,INCRLATCH,DECRLATCH, SP0OUT,SP1OUT,WRSP0,WRSP1,WRZ,WRW,WZOUT,WRWZ: bit; Signal RESETBAR_buf,INSTRESET: bit; signal S0_buf,S1_buf,IOMBAR_buf,RDBAR_buf,WRBAR_buf: bit; begin IR : INST_REG port map(I5,I4,I3,I2,I1,I0,ID(19 downto 0), DIN(7 downto 0),INA,RESETBAR_buf,M1,T3,CLK,GND); DA : DATAADDR port map(AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7, A8, A9, A10,A11,A12,A13,A14,A15, B8BO(0 to 7), B8BIN(0 to 7), B16BIN(0 to 15), DIN(7 downto 0), MDROUT, S0_buf, S1_buf, IOMBAR_buf,BIMC,RDBAR_buf,WRBAR_buf,T1,T3,T4,T6,CLKOUT_buf,VCC); RPD : regpad port map(B16BO(0 to 15), B8BO(0 to 7), B16BIN(0 to 15), B8BIN(0 to 7), SEL16BUS,SEL_CNTR,WRB,WRC,WRBC,WRPCH,WRPCL,WRPC, BOUT,COUT,BCOUT,PCHOUT,PCLOUT,PCOUT,RESETBAR_buf, WRH,WRL, WRHL,WRD,WRE,WRDE,HOUT,LOUT,HLOUT,DOUT,EOUT,DEOUT, ID(19),ID(13),ID(3),LOADLATCH,ENLATCHOUT, INCRLATCH,DECRLATCH,SP0OUT,SP1OUT,SPOUT,WRSP0,WRSP1,WRSP, CLK,CLKOUT_buf,WRZ,WRW,WZOUT,WRWZ,T4,GND,VCC); RGC : reg_ctrl port map(WRPC,LOADLATCH,INCRLATCH,PCOUT,PCHOUT, PCLOUT,WRPCL,WRPCH,DECRLATCH,SEL16BUS,SEL_CNTR,SPOUT, ENLATCHOUT,HOUT,LOUT,WRL,WRH,WRB,WRC,WRD,WRE,WRSP0,WRSP1, BOUT,COUT,DOUT,EOUT,SP0OUT,SP1OUT,WRAUXACC, WRSP,WRBC,WRHL,WRDE,HLOUT,BCOUT,DEOUT,WR2TEMP, ACCOUTEN,WRACC,ALUOUTEN,WRZ,WRW,WZOUT,WRWZ,ENBUSTOAUX,TEMP_OUT, I5,I4,I3,I2,I1,I0,VCC,GND,M1,M2,M3,M4,M5, T1,T2,T3,T4,T5,T6,CC6,LASTMC,INA,CC,CCBAR,MDROUT, ID(0), ID(1), ID(2), ID(3), ID(4), ID(5), ID(6), ID(7), ID(8), ID(9), ID(10),ID(11),ID(12),ID(13),ID(14),ID(15),ID(16),ID(17),ID(18),ID(19)); C1 : ctl_lgc1 port map(INSTRESET,lastmc,RSTN,ALE,RDBAR_buf,WRBAR_buf,INTABAR, IOMBAR_buf,S1_buf,S0_buf,BIMC,CC6, ID(19 downto 0), CC,CCbar,I2,I3,I5,M5,M4,M3,M2,M1, T1,T2,T3,CLKOUT_buf,CLK,VCC,INA,INTA,RESETBAR_buf); C2 : ctl_lgc2 port map(M5,M4,M3,M2,M1,RESETBAR_buf, T1,T2,T3,T4,T5,T6, RESETOUT,HLDA,CLK,RESETINBAR, INSTRESET,HOLD,READY,VINT,CC6,BIMC,ID(17),ID(14), ID(6),GND,VCC,CLKOUT_buf,THALT,THOLD,TWAIT); IT : INTERUPT port map(B16BO(0 to 15),B8BO(0 to 7), B8BIN(6 to 7),B8BIN(0 to 4), INA,SOD,INTA,VINT,TRAP,RST75,RST65,RST55,INTR, RESETBAR_buf,CLK,ID(19),ID(16),ID(14),ID(12),ID(3),ID(0), THALT,THOLD,T5,T4,T3,T2,CC6,LASTMC,CLKOUT_buf,SID, I5,I4,I3,M3,M1,RSTN,VCC,GND); AL : ALULOGIC port map( B8BO(7),B8BO(6),B8BO(5),B8BO(4),B8BO(3),B8BO(2),B8BO(1),B8BO(0), B8BIN(7),B8BIN(6),B8BIN(5),B8BIN(4),B8BIN(3),B8BIN(2),B8BIN(1),B8BIN(0), WRACC,ACCOUTEN,WRAUXACC,WR2TEMP,TEMP_OUT,CC,CCBAR, ID(19),ID(18),ID(16 downto 4),ID(1),I5,I4,I3, M3,M2,M1,T4,T3,T2,VCC,GND,CLK,ALUOUTEN,RESETBAR_buf,ENBUSTOAUX); -- The OCNANDs connected to the outputs of the various registers invert -- the bus signals. These inverters restore the correct polarity. BUS_INV1 : INV8 port map(B16BIN(0 to 7), B16BO(0 to 7)); BUS_INV2 : INV8 port map(B16BIN(8 to 15), B16BO(8 to 15)); BUS_INV3 : INV8 port map(B8BIN(0 to 7), B8BO(0 to 7)); T9 : inv_gate generic map (1,1) port map(CLKOUT_buf,CLK); buf0 : buf_gate port map(S0,S0_buf); buf1 : buf_gate port map(S1,S1_buf); buf2 : buf_gate port map(IOMBAR,IOMBAR_buf); buf3 : buf_gate port map(RDBAR,RDBAR_buf); buf4 : buf_gate port map(WRBAR,WRBAR_buf); buf5 : buf_gate port map (CLKOUT,CLKOUT_buf); end structure;