--
-- Rcsid[] = "$Id: dataaddr.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

--  This module contains the (MDR) memory data register
--  and the (MAR) memory address register logic.

entity dataaddr is
port(AD: out bit_vector(0 to 7);
     A:  out bit_vector(8 to 15);
     B8BO: out bit_vector(0 to 7);
     B8BIN: in bit_vector(0 to 7);
     B16BIN: in bit_vector(0 to 15);
     DIN7,DIN6,DIN5,DIN4,DIN3,DIN2,DIN1,DIN0: in bit;
     MDROUT: out bit;
     S0,S1,IOMBAR,BIMC,RDBAR,WRBAR,T1,T3,T4,T6,CLK,VCC: in bit);
end;

architecture structure of dataaddr is

component reg_8bit
port(Q: out bit_vector(0 to 7);
     D: in bit_vector(0 to 7);
     CK, WRENABLE, CLEAR, PRESET: in bit);
end component;

component mux_4bit
port(Y: out bit_vector(0 to 3);
     A,B: in bit_vector(0 to 3);
     choose: in bit);
end component;

component ocnand
port(O: out bit_vector(7 downto 0);
     I: in bit_vector(7 downto 0);
     ENABLE: in bit);
end component;

component buf8
port(BUF_OUT: out bit_vector(7 downto 0);
	 BUF_IN:  in  bit_vector(7 downto 0));
end component;

signal n1, n6, n7, n9: bit;
signal n12,n13: bit;
signal d: bit_vector(0 to 7);
signal m0, m1: bit_vector(0 to 3);
signal AD_buf: bit_vector(0 to 7);
signal MDROUT_buf: bit;

begin
MDR : REG_8BIT port map(AD_buf(0 to 7),d(0 to 7),n7,VCC,VCC,VCC);
U0 : buf8 port map(AD(0 to 7), AD_buf(0 to 7));
U1 : mux_4bit port map(d(0 to 3), DIN0,DIN1,DIN2,DIN3, m0(0 to 3), RDBAR);
U2 : mux_4bit port map(d(4 to 7), DIN4,DIN5,DIN6,DIN7, m1(0 to 3), RDBAR);
U3 : mux_4bit port map(m0(0 to 3),B16BIN(0 to 3),B8BIN(0 to 3),n6);
U4 : mux_4bit port map(m1(0 to 3),B16BIN(4 to 7),B8BIN(4 to 7),n6);
U5 : OCNAND port map(B8BO(0 to 7),AD_buf(0 to 7),MDROUT_buf);

U6 : and_gate generic map(1,1) port map(n6,T4,T3,T6);
U7 : nand_gate generic map(1,1) port map(n7,T1,n9,WRBAR);
U9 : or_gate generic map(1,1) port map(n9,RDBAR,CLK);
U11 : nor_gate generic map(1,1) port map(MDROUT_buf,BIMC,T3,n12);
U11a : buf_gate port map (MDROUT,MDROUT_buf);
U12 : nand_gate generic map(1,1) port map(n12,S1,n13);
U13 : nand_gate generic map(1,1) port map(n13,IOMBAR,S0);
MAR : REG_8BIT port map(A(8 to 15),B16BIN(8 to 15),n1,VCC,VCC,VCC);
U17 : inv_gate generic map(1,1) port map(n1,T1);
end structure;

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