--
-- Rcsid[] = "$Id: alu_ctrl.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

---------------------------------------------
-- alu_ctrl.vhd
-- June 19, 1993
---------------------------------------------

--  This module generates control signals for the 74181 ALU functions,
--  based on the instruction selected.  It also generates carry signals
--  to feed into the 74181 Cn input, depending on the content of the
--  carry flag and the instruction.

entity alu_ctrl is
port(M,S0,S1,S2,S3,ENABLEDCY: out bit;
     ID1,ID4,ID6,ID7,ID8,ID9,ID10,ID11,ID12,
     ID13,ID14,ID15,ID16,ID18,ID19,I3,M3,CY,ID5: in bit);
end;

architecture structure of alu_ctrl is

signal n0, n0A, n2, n5, n6, n7, n7A, n9, n10: bit;
signal n17A, n22, n28, n29, n35 : bit;
signal n35a, n35b, n37, n37a,n38a: bit;
signal n41, n44, n45, n46, n52 : bit;
signal DOSUB, DOSBB, DOADD, DOAND, DOXOR : bit;
signal S0B, S1B, S2B, S3B, S0N, S1N, S2N, S3N: bit;
signal ROT, CMA, ALU_OPS: bit;

begin
U0 : or_gate generic map(1,1) port map(n0,ALU_OPS,n0A);
U0A : AND_gate port map(n0A,ID8,ID9);
U2 : or_gate generic map(1,1) port map(n2,ID16,ID4);       -- INR
U5 : or_gate generic map(1,1) port map(n5,ID16,ID1,n22);   -- DAD
U6 : or_gate generic map(1,1) port map(n6,ID16,ID12,ID7);  -- DAA
U7 : and_gate generic map(1,1) port map(n7,n7A,I3);
U7A : NAND_gate port map(n7A,ID18,ID19);  -- lower right quadrant of op-code map
U9 : nor_gate generic map(1,1) port map(n9,M3,n5);
U10 : or_gate generic map(1,1) port map(n10,n7,n9);        -- ADD CARRY
U11 : NAND_gate generic map(1,1) port map(DOADD,n0,n45);
U17 : NOR_gate generic map(1,1) port map(DOSUB,ALU_OPS,n17A);
U17A : AND_gate port map(n17A,ID10,ID11,ID15);
U20 : NOR_gate generic map(1,1) port map(DOAND,ID12,ALU_OPS);
U22 : inv_gate generic map(1,1) port map(n22,I3);
U23 : NOR_gate generic map(1,1) port map(DOXOR,ID13,ALU_OPS);
U28 : and_gate generic map(1,1) port map(n28,DOADD,CY,n10);
U29 : and_gate generic map(1,1) port map(n29,DOSBB,CY);
u29a : NOR_gate generic map(1,1) port map(DOSBB,ALU_OPS,ID11);
U30 : or_gate generic map(1,1) port map(ENABLEDCY,n28,n29,n41);
U35 : or_gate generic map(1,1) port map(n35,n35a,n37a);
U35a : OR_gate generic map(1,1) port map(n35a,ALU_OPS,n35b);
U35b : AND_gate generic map(1,1) port map(n35b,ID13,ID14,n17A);
U37 : NAND_gate generic map(1,1) port map(n37,n35a,n37a);
u37a : OR_gate generic map(1,1) port map(n37a,DOAND,DOADD);
U41 : Nor_gate generic map(1,1) port map(n41,ID16,ID5); -- for DCR INSTRUCTIONS
U42 : NOR_gate generic map(1,1) port map(M,DOSUB,DOADD,n41);
U44 : or_gate generic map(1,1) port map(n44,ID19,ID6);
U45 : AND_gate generic map(1,1) port map(n45,n2,n5,n6);
U46 : Nand_gate generic map(1,1) port map(n46,ALU_OPS,n45);

U48 : and_gate generic map(1,1) port map(S0B,n35,n46);
U36 : or_gate  generic map(1,1) port map(S1B,n37,DOAND);
U49 : and_gate generic map(1,1) port map(S2B,n37,n46);
U38 : or_gate  generic map(1,1) port map(S3B,DOADD,n38a);
u38a : NOR_gate generic map(1,1) port map(n38a,DOXOR,DOSUB);

U51 : and_gate generic map(1,1) port map(n52,ID8,ID9,ID10,ID11,ID14,ID15);
U50 : NOR_gate generic map(1,1) port map(ROT,ID16,ID7,n52);
U52a : OR_gate  generic map(1,1) port map(S0N,ROT,S0B);
U52b : BUF_gate generic map(1,1) port map(S1N,S1B);
U52c : OR_gate  generic map(1,1) port map(S2N,ROT,S2B);
U52d : BUF_gate generic map(1,1) port map(S3N,S3B);

U54 : or_gate generic map(1,1) port map(CMA,ID16,ID7,ID13);  -- CMA
U53a : BUF_gate generic map(1,1) port map(S0,S0N);
U53b : AND_gate generic map(1,1) port map(S1,CMA,S1N);
U53c : BUF_gate generic map(1,1) port map(S2,S2N);
U53d : AND_gate generic map(1,1) port map(S3,CMA,S3N);
U100 : and_gate generic map(1,1) port map(ALU_OPS,ID18,n44);
end structure;

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