-- -- Rcsid[] = "$Id: alu_8bit.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $"; -- -- This component has two 74181s connected to form an 8-bit -- ALU. This component also includes the parity1 generator. entity ALU_8BIT is port( F: out bit_vector(7 downto 0); A_eq_B, X, Y, Z, AC, P, CY: out bit; S: in bit_vector(3 downto 0); A: in bit_vector(7 downto 0); B: in bit_vector(7 downto 0); Cn, M: in bit ); end; architecture structure of ALU_8BIT is component sn54181 port(F3, F2, F1, F0: out bit; A_EQ_B, X, Cn4, Y: out bit; S3, S2, S1, S0: in bit; A3, A2, A1, A0: in bit; B3, B2, B1, B0: in bit; M, Cn: in bit); end component; component parity1 port(A, B, C, D, E, F, G, H: in bit; EVEN : out bit); end component; component buf8 port(BUF_OUT: out bit_vector(7 downto 0); BUF_IN: in bit_vector(7 downto 0)); end component; signal net1, net2, net3, net4, net5, net6: bit; signal F_buf: bit_vector(7 downto 0); begin -- components U1 thru U4 are used to make the connection between the -- two 4-bit ALUs used as subcomponents (for purposes of carry) U0 : inv_gate generic map(2,2) port map(AC,net6); U1 : inv_gate generic map(2,2) port map(net1,Cn); U2 : and_gate generic map(2,2) port map(net2,net1,net5); U3 : and_gate generic map(2,2) port map(net3,net4,net5); U4 : nor_gate generic map(2,2) port map(net6,net2,net3); -- U5 and U6 are the 4-bit ALUs used to create an 8-bit system U5 : sn54181 port map(F_buf(3 downto 0),OPEN,net4,OPEN,net5, S(3 downto 0),A(3 downto 0),B(3 downto 0),M,Cn); U6 : sn54181 port map(F_buf(7 downto 4),A_eq_B,X,CY,Y, S(3 downto 0),A(7 downto 4),B(7 downto 4),M,net6); U7 : buf8 port map(F(7 downto 0), F_buf(7 downto 0)); -- ZEROCK is the input to the zero flag of the flag register ZEROCK : nor_gate generic map(2,2) port map(Z,F_buf(7 downto 0)); -- PARITYCK is the input to the parity1 bit of the flag register PARITYCK : parity1 port map(F_buf(7 downto 0),P); -- F7 will be used to set the sign. end structure;