--
-- Rcsid[] = "$Id: acc_ctrl.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

---------------------------------------------
-- acc_ctrl.vhd
-- June 19, 1993
---------------------------------------------

-- This component generates 'ACCWR' and 'ACCOUTEN' signals
-- in appropriate T states, to write into the accumulator
-- and to enable the accumulator outputs on to the 8 bit bus.

entity acc_ctrl is
port(ACCWR, ACCOUTEN: out bit;
     ID0,  ID1,  ID2,  ID3,  ID5,  ID6,  ID7,  ID8,  ID9:  in bit;
     ID10, ID11, ID12, ID13, ID14, ID15, ID16, ID18, ID19: in bit;
     M1, M2, M3, M4, T1, T2, T3, T4: in bit);
end;

architecture structure of acc_ctrl is

signal n0, n1, n2, n3, n4, n7: bit;
signal n9, n11, LDAX, n14, n15, POP_PSW, n17, n18: bit;
signal IN_IO, n20, SIM, n22, n23, PUSH_PSW, n25, n26, n27, n28, n29: bit;
signal n71: bit;

begin
-- ENABLE ACCWR IN M1.T2
U0 : inv_gate generic map(1,1) port map(n0,ID15);       -- exclude CMP instructions
U1 : or_gate generic map(1,1) port map(n1,ID18,n0);     -- all ADD and SUB instructions
U2 : and_gate generic map(1,1) port map(n2,n1,n4,n7,n9);
U3 : or_gate generic map(1,1) port map(n3,M1,T2,n2);
U4 : or_gate generic map(1,1) port map(n4,n0,ID19,ID6); -- all ADD and SUB immediate instructions
U7 : or_gate generic map(1,1) port map(n7,ID16,ID7,n71);
U71 : and_gate generic map(1,1) port map(n71,n28,ID13);
U9 : or_gate generic map(1,1) port map(n9,ID0,ID12,ID16);

-- ENABLE LDAX
U11 : and_gate generic map(1,1) port map(n11,ID9,ID11);
U12 : or_gate generic map(1,1) port map(LDAX,ID16,ID2,n11,M2,T3);
U13 : NAND_gate generic map(1,1) port map(ACCWR,n3,LDAX,n15,n18,n20);  -- output

-- LDA
U14 : buf_gate generic map(1,1) port map(n14,ID15);
U15 : or_gate generic map(1,1) port map(n15,M4,T3,n14);

-- POP PSW & INport
U16 : or_gate generic map(1,1) port map(POP_PSW,ID19,ID14,ID1);
U17 : and_gate generic map(1,1) port map(n17,POP_PSW,IN_IO);
U18 : or_gate generic map(1,1) port map(n18,n17,M3,T3);
U19 : or_gate generic map(1,1) port map(IN_IO,ID19,ID3,ID11);

-- DAA instruction
U20 : or_gate generic map(1,1) port map(n20,ID16,ID12,ID7,M1,T4);

-- ACCOUT ENABLE
U21 : or_gate generic map(1,1) port map(SIM,ID16,ID14,ID0);
U22 : nor_gate generic map(1,1) port map(n22,SIM,M1,T2);
U23 : or_gate generic map(1,1) port map(n23,ID14,M4);          --  STA
U24 : or_gate generic map(1,1) port map(PUSH_PSW,ID19,ID14,ID5,M2); --  PUSH PSW
U25 : or_gate generic map(1,1) port map(n25,ID19,ID10,ID3,M3); --  OUT PORT
U26 : nand_gate generic map(1,1) port map(n26,n23,PUSH_PSW,n25,n27);
U27 : or_gate generic map(1,1) port map(n27,ID16,ID7,M1,n28);
U28 : and_gate generic map(1,1) port map(n28,ID8,ID9,ID10,ID11);
U29 : AND_gate generic map(1,1) port map(n29,T1,n26);
U31 : or_gate generic map(1,1) port map(ACCOUTEN,n22,n29);
end structure;

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