------------------------------------------------------------------------------- -- EE 126 Project # 1, Serial Arithmetic and Logic Unit, part 2 -- VHDL implementation by: Frank Bruno -- Part of a project for Professor Chang ------------------------------------------------------------------------------- ENTITY alu_2 IS PORT(opcode : IN bit_vector(2 DOWNTO 0); bin : IN bit_vector(3 DOWNTO 0); load : IN bit; clock : IN bit; areg : BUFFER bit_vector(3 DOWNTO 0); breg : BUFFER bit_vector(3 DOWNTO 0); carry : BUFFER bit); END alu_2; ARCHITECTURE behave_alu_2 OF alu_2 IS BEGIN -- behave_alu_2 PROCESS VARIABLE a : bit; VARIABLE b : bit; VARIABLE cin : bit; VARIABLE s : bit; VARIABLE cout : bit; BEGIN -- PROCESS WAIT UNTIL clock'EVENT and clock = '1'; IF (load = '1') THEN breg <= bin; areg <= "0000"; ELSE a := areg(0); areg(0) <= areg(1); areg(1) <= areg(2); areg(2) <= areg(3); b := breg(0); breg(0) <= breg(1); breg(1) <= breg(2); breg(2) <= breg(3); breg(3) <= b; cin := carry; CASE opcode IS WHEN "000" => -- clear, s <= 0 s := '0'; WHEN "001" => -- compliment, s <= a' s := NOT(a); WHEN "010" => -- increment, s <= a+cin s := a XOR cin; cout := a AND cin; WHEN "011" => -- negate, s <= a' + cin s := NOT(a XOR cin); cout := (NOT(a)) AND cin; WHEN "100" => -- transfer b, s <= b s := b; WHEN "101" => -- XOR, a XOR b s := a XOR b; WHEN "110" => -- Add, a + b + cin s := (a XOR b) XOR cin; cout := (a AND cin) OR (b AND (a XOR cin)); WHEN "111" => -- Subtract, a + b' + cin s := a XOR (NOT(b)) XOR cin; cout := (a AND cin) OR ((NOT(b)) AND (a XOR cin)); WHEN OTHERS => END CASE; -- opcode areg(3) <= s; carry <= cout; END IF; END PROCESS; END behave_alu_2;