Library IEEE; use IEEE.std_logic_1164.all; entity testenv is end; architecture tb of testenv is signal clk, reset : std_logic; signal nickel_in : boolean; signal nickel_out : boolean; signal dime_in : boolean; signal dime_out : boolean; signal quarter_in : boolean; signal dispense : boolean; component drink port (clk, reset : in std_logic := '0'; nickel_in, dime_in, quarter_in : in boolean; nickel_out, dime_out, dispense : out boolean); end component; begin uut: drink port map (clk, reset, nickel_in, dime_in, quarter_in, nickel_out, dime_out, dispense); -- clock stimuli of 100 ns time period clk_p: process begin clk <= '0', '1' after 50 ns; wait for 100 ns; end process; -- reset input stimuli rst_p: process begin wait for 10 ns; reset <= '1'; wait on reset; end process; end tb; configuration cfg_testenv of testenv is for tb -- for uut: drink use entity work.drink(syn_behav); for uut: drink use entity work.drink(behav); end for; end for; end;