Library IEEE; use IEEE.std_logic_1164.all; entity drink is port(clk, reset : in std_logic; nickel_in, dime_in, quarter_in : in boolean; nickel_out, dime_out, dispense : out boolean); end; architecture behav of drink is type state_type is (idle, five, ten, fifteen, twenty, twenty_five, thirty, owe_dime); signal current_state, next_state: state_type; begin log_p: process(current_state, nickel_in, dime_in, quarter_in) begin -- Default assignments next_state <= current_state; nickel_out <= false; dime_out <= false; dispense <= false; -- State transitions and output logic case current_state is when idle => if(nickel_in) then next_state <= five; elsif(dime_in) then next_state <= ten; elsif(quarter_in) then next_state <= twenty_five; end if; when five => if(nickel_in) then next_state <= ten; elsif(dime_in) then next_state <= fifteen; elsif(quarter_in) then next_state <= thirty; end if; when ten => if(nickel_in) then next_state <= fifteen; elsif(dime_in) then next_state <= twenty; elsif(quarter_in) then next_state <= idle; dispense <= true; end if; when fifteen => if(nickel_in) then next_state <= twenty; elsif(dime_in) then next_state <= twenty_five; elsif(quarter_in) then next_state <= idle; dispense <= true; nickel_out <= true; end if; when twenty => if(nickel_in) then next_state <= twenty_five; elsif(dime_in) then next_state <= thirty; elsif(quarter_in) then next_state <= idle; dispense <= true; dime_out <= true; end if; when twenty_five => if(nickel_in) then next_state <= thirty; elsif(dime_in) then next_state <= idle; dispense <= true; elsif(quarter_in) then next_state <= idle; dispense <= true; dime_out <= true; nickel_out <= true; end if; when thirty => if(nickel_in) then next_state <= idle; dispense <= true; elsif(dime_in) then next_state <= idle; dispense <= true; nickel_out <= true; elsif(quarter_in) then next_state <= owe_dime; dispense <= true; dime_out <= true; end if; when owe_dime => next_state <= idle; dime_out <= true; end case; end process; -- Synchronize state value with clock. -- This causes it to be stored in flip flops -- The asynchronous reset forces the idle-state reg_p: process(clk, reset) begin if reset = '0' then current_state <= idle; elsif clk'event and clk = '1' then current_state <= next_state; end if; end process; end behav;