LIBRARY ieee; use ieee.std_logic_1164.all; LIBRARY exemplar ; use exemplar.exemplar_1164.all; package my_stuff is procedure dff(signal input: IN integer; signal clk: IN std_logic; signal output: OUT integer); procedure dff_enable( signal input: IN integer; signal enable,clk: IN std_logic; signal output: OUT integer); procedure dff_enable( signal input: IN std_logic; signal enable,clk: IN std_logic; signal output: OUT std_logic); procedure dff_enable( signal input: IN std_logic_vector; signal enable,clk: IN std_logic; signal output: OUT std_logic_vector); component rm32x8h port ( D: in std_logic_vector(7 downto 0); A: in std_logic_vector(4 downto 0); O: out std_logic_vector(7 downto 0); WE: in std_logic ); end component ; end my_stuff; package body my_stuff is procedure dff( signal input : IN integer; signal clk: IN std_logic; signal output : OUT integer ) is begin if (clk'event and clk='1') then output <= input; end if; end dff; procedure dff_enable ( signal input : IN integer; signal enable, clk: IN std_logic; signal output : OUT integer ) is begin if (clk'event and clk='1') then if (enable='1') then output <= input; end if; end if; end dff_enable; procedure dff_enable ( signal input : IN std_logic; signal enable, clk: IN std_logic; signal output : OUT std_logic ) is begin if (clk'event and clk='1') then if (enable='1') then output <= input; end if; end if; end dff_enable; procedure dff_enable ( signal input : IN std_logic_vector; signal enable, clk: IN std_logic; signal output : OUT std_logic_vector ) is begin if (clk'event and clk='1') then if (enable='1') then output <= input; end if; end if; end dff_enable; end my_stuff;